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375 lines
11 KiB
C
375 lines
11 KiB
C
/* crc32c.c -- compute CRC-32C using the Intel crc32 instruction
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* Copyright (C) 2013 Mark Adler
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* Version 1.1 1 Aug 2013 Mark Adler
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*/
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/*
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This software is provided 'as-is', without any express or implied
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warranty. In no event will the author be held liable for any damages
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arising from the use of this software.
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Permission is granted to anyone to use this software for any purpose,
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including commercial applications, and to alter it and redistribute it
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freely, subject to the following restrictions:
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1. The origin of this software must not be misrepresented; you must not
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claim that you wrote the original software. If you use this software
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in a product, an acknowledgment in the product documentation would be
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appreciated but is not required.
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2. Altered source versions must be plainly marked as such, and must not be
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misrepresented as being the original software.
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3. This notice may not be removed or altered from any source distribution.
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Mark Adler
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madler@alumni.caltech.edu
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*/
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/* Use hardware CRC instruction on Intel SSE 4.2 processors. This computes a
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CRC-32C, *not* the CRC-32 used by Ethernet and zip, gzip, etc. A software
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version is provided as a fall-back, as well as for speed comparisons. */
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/* Version history:
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1.0 10 Feb 2013 First version
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1.1 1 Aug 2013 Correct comments on why three crc instructions in parallel
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <unistd.h>
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#include "crc32c.h"
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/* CRC-32C (iSCSI) polynomial in reversed bit order. */
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#define POLY 0x82f63b78
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/* Table for a quadword-at-a-time software crc. */
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static __thread int crc32_sw_init = 0;
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static uint32_t crc32c_table[8][256];
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/* Construct table for software CRC-32C calculation. */
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static void crc32c_init_sw(void)
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{
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uint32_t n, crc, k;
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crc32_sw_init = 1;
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for (n = 0; n < 256; n++)
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{
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crc = n;
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crc = crc & 1 ? (crc >> 1) ^ POLY : crc >> 1;
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crc = crc & 1 ? (crc >> 1) ^ POLY : crc >> 1;
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crc = crc & 1 ? (crc >> 1) ^ POLY : crc >> 1;
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crc = crc & 1 ? (crc >> 1) ^ POLY : crc >> 1;
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crc = crc & 1 ? (crc >> 1) ^ POLY : crc >> 1;
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crc = crc & 1 ? (crc >> 1) ^ POLY : crc >> 1;
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crc = crc & 1 ? (crc >> 1) ^ POLY : crc >> 1;
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crc = crc & 1 ? (crc >> 1) ^ POLY : crc >> 1;
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crc32c_table[0][n] = crc;
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}
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for (n = 0; n < 256; n++)
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{
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crc = crc32c_table[0][n];
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for (k = 1; k < 8; k++)
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{
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crc = crc32c_table[0][crc & 0xff] ^ (crc >> 8);
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crc32c_table[k][n] = crc;
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}
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}
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}
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/* Table-driven software version as a fall-back. This is about 15 times slower
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than using the hardware instructions. This assumes little-endian integers,
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as is the case on Intel processors that the assembler code here is for. */
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static uint32_t crc32c_sw(uint32_t crci, const void *buf, size_t len)
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{
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const unsigned char *next = (const unsigned char*)buf;
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uint64_t crc;
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if (!crc32_sw_init)
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crc32c_init_sw();
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crc = crci ^ 0xffffffff;
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while (len && ((uintptr_t)next & 7) != 0)
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{
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crc = crc32c_table[0][(crc ^ *next++) & 0xff] ^ (crc >> 8);
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len--;
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}
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while (len >= 8)
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{
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crc ^= *(uint64_t *)next;
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crc = crc32c_table[7][crc & 0xff] ^
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crc32c_table[6][(crc >> 8) & 0xff] ^
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crc32c_table[5][(crc >> 16) & 0xff] ^
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crc32c_table[4][(crc >> 24) & 0xff] ^
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crc32c_table[3][(crc >> 32) & 0xff] ^
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crc32c_table[2][(crc >> 40) & 0xff] ^
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crc32c_table[1][(crc >> 48) & 0xff] ^
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crc32c_table[0][crc >> 56];
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next += 8;
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len -= 8;
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}
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while (len)
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{
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crc = crc32c_table[0][(crc ^ *next++) & 0xff] ^ (crc >> 8);
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len--;
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}
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return (uint32_t)crc ^ 0xffffffff;
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}
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/* Multiply a matrix times a vector over the Galois field of two elements,
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GF(2). Each element is a bit in an unsigned integer. mat must have at
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least as many entries as the power of two for most significant one bit in
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vec. */
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static inline uint32_t gf2_matrix_times(uint32_t *mat, uint32_t vec)
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{
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uint32_t sum;
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sum = 0;
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while (vec)
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{
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if (vec & 1)
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sum ^= *mat;
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vec >>= 1;
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mat++;
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}
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return sum;
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}
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/* Multiply a matrix by itself over GF(2). Both mat and square must have 32
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rows. */
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static inline void gf2_matrix_square(uint32_t *square, uint32_t *mat)
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{
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int n;
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for (n = 0; n < 32; n++)
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square[n] = gf2_matrix_times(mat, mat[n]);
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}
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/* Construct an operator to apply len zeros to a crc. len must be a power of
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two. If len is not a power of two, then the result is the same as for the
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largest power of two less than len. The result for len == 0 is the same as
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for len == 1. A version of this routine could be easily written for any
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len, but that is not needed for this application. */
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static void crc32c_zeros_op(uint32_t *even, size_t len)
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{
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int n;
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uint32_t row;
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uint32_t odd[32]; /* odd-power-of-two zeros operator */
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/* put operator for one zero bit in odd */
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odd[0] = POLY; /* CRC-32C polynomial */
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row = 1;
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for (n = 1; n < 32; n++)
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{
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odd[n] = row;
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row <<= 1;
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}
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/* put operator for two zero bits in even */
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gf2_matrix_square(even, odd);
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/* put operator for four zero bits in odd */
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gf2_matrix_square(odd, even);
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/* first square will put the operator for one zero byte (eight zero bits),
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in even -- next square puts operator for two zero bytes in odd, and so
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on, until len has been rotated down to zero */
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do
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{
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gf2_matrix_square(even, odd);
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len >>= 1;
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if (len == 0)
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return;
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gf2_matrix_square(odd, even);
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len >>= 1;
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} while (len);
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/* answer ended up in odd -- copy to even */
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for (n = 0; n < 32; n++)
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even[n] = odd[n];
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}
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/* Take a length and build four lookup tables for applying the zeros operator
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for that length, byte-by-byte on the operand. */
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static void crc32c_zeros(uint32_t zeros[][256], size_t len)
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{
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uint32_t n;
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uint32_t op[32];
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crc32c_zeros_op(op, len);
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for (n = 0; n < 256; n++)
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{
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zeros[0][n] = gf2_matrix_times(op, n);
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zeros[1][n] = gf2_matrix_times(op, n << 8);
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zeros[2][n] = gf2_matrix_times(op, n << 16);
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zeros[3][n] = gf2_matrix_times(op, n << 24);
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}
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}
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/* Apply the zeros operator table to crc. */
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static inline uint32_t crc32c_shift(uint32_t zeros[][256], uint32_t crc)
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{
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return zeros[0][crc & 0xff] ^ zeros[1][(crc >> 8) & 0xff] ^
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zeros[2][(crc >> 16) & 0xff] ^ zeros[3][crc >> 24];
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}
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/* Block sizes for three-way parallel crc computation. LONG and SHORT must
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both be powers of two. The associated string constants must be set
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accordingly, for use in constructing the assembler instructions. */
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#define LONG 8192
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#define LONGx1 "8192"
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#define LONGx2 "16384"
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#define SHORT 256
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#define SHORTx1 "256"
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#define SHORTx2 "512"
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/* Tables for hardware crc that shift a crc by LONG and SHORT zeros. */
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static __thread int crc32c_hw_init = 0;
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static uint32_t crc32c_long[4][256];
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static uint32_t crc32c_short[4][256];
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/* Initialize tables for shifting crcs. */
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static void crc32c_init_hw(void)
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{
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crc32c_hw_init = 1;
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crc32c_zeros(crc32c_long, LONG);
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crc32c_zeros(crc32c_short, SHORT);
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}
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/* Compute CRC-32C using the Intel hardware instruction. */
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static uint32_t crc32c_hw(uint32_t crc, const void *buf, size_t len)
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{
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#ifndef __x86_64__
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return 0;
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#else
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const unsigned char *next = (const unsigned char*)buf;
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const unsigned char *end;
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uint64_t crc0, crc1, crc2; /* need to be 64 bits for crc32q */
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/* populate shift tables the first time through */
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if (!crc32c_hw_init)
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crc32c_init_hw();
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/* pre-process the crc */
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crc0 = crc ^ 0xffffffff;
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/* compute the crc for up to seven leading bytes to bring the data pointer
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to an eight-byte boundary */
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while (len && ((uintptr_t)next & 7) != 0)
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{
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__asm__(
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"crc32b\t" "(%1), %0"
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: "=r"(crc0)
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: "r"(next), "0"(crc0)
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);
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next++;
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len--;
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}
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/* compute the crc on sets of LONG*3 bytes, executing three independent crc
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instructions, each on LONG bytes -- this is optimized for the Nehalem,
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Westmere, Sandy Bridge, and Ivy Bridge architectures, which have a
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throughput of one crc per cycle, but a latency of three cycles */
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while (len >= LONG*3)
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{
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crc1 = 0;
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crc2 = 0;
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end = next + LONG;
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do
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{
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__asm__(
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"crc32q\t" "(%3), %0\n\t"
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"crc32q\t" LONGx1 "(%3), %1\n\t"
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"crc32q\t" LONGx2 "(%3), %2"
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: "=r"(crc0), "=r"(crc1), "=r"(crc2)
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: "r"(next), "0"(crc0), "1"(crc1), "2"(crc2)
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);
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next += 8;
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} while (next < end);
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crc0 = crc32c_shift(crc32c_long, crc0) ^ crc1;
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crc0 = crc32c_shift(crc32c_long, crc0) ^ crc2;
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next += LONG*2;
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len -= LONG*3;
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}
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/* do the same thing, but now on SHORT*3 blocks for the remaining data less
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than a LONG*3 block */
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while (len >= SHORT*3)
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{
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crc1 = 0;
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crc2 = 0;
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end = next + SHORT;
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do
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{
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__asm__(
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"crc32q\t" "(%3), %0\n\t"
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"crc32q\t" SHORTx1 "(%3), %1\n\t"
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"crc32q\t" SHORTx2 "(%3), %2"
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: "=r"(crc0), "=r"(crc1), "=r"(crc2)
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: "r"(next), "0"(crc0), "1"(crc1), "2"(crc2)
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);
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next += 8;
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} while (next < end);
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crc0 = crc32c_shift(crc32c_short, crc0) ^ crc1;
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crc0 = crc32c_shift(crc32c_short, crc0) ^ crc2;
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next += SHORT*2;
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len -= SHORT*3;
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}
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/* compute the crc on the remaining eight-byte units less than a SHORT*3
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block */
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end = next + (len - (len & 7));
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while (next < end)
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{
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__asm__(
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"crc32q\t" "(%1), %0"
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: "=r"(crc0)
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: "r"(next), "0"(crc0)
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);
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next += 8;
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}
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len &= 7;
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/* compute the crc for up to seven trailing bytes */
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while (len)
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{
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__asm__(
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"crc32b\t" "(%1), %0"
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: "=r"(crc0)
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: "r"(next), "0"(crc0)
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);
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next++;
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len--;
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}
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/* return a post-processed crc */
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return (uint32_t)crc0 ^ 0xffffffff;
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#endif
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}
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/* Check for SSE 4.2. SSE 4.2 was first supported in Nehalem processors
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introduced in November, 2008. This does not check for the existence of the
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cpuid instruction itself, which was introduced on the 486SL in 1992, so this
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will fail on earlier x86 processors. cpuid works on all Pentium and later
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processors. */
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#define SSE42(have) \
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do { \
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uint32_t eax, ecx; \
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eax = 1; \
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__asm__("cpuid" \
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: "=c"(ecx) \
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: "a"(eax) \
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: "%ebx", "%edx"); \
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(have) = (ecx >> 20) & 1; \
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} while (0)
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/* Compute a CRC-32C. If the crc32 instruction is available, use the hardware
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version. Otherwise, use the software version. */
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uint32_t crc32c(uint32_t crc, const void *buf, size_t len)
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{
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#ifndef __x86_64__
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return crc32c_sw(crc, buf, len);
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#else
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int sse42;
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SSE42(sse42);
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return sse42 ? crc32c_hw(crc, buf, len) : crc32c_sw(crc, buf, len);
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#endif
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}
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