420 lines
10 KiB
C
420 lines
10 KiB
C
/*-
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*******************************************************************************
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Copyright (C) 2015 Annapurna Labs Ltd.
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This file may be licensed under the terms of the Annapurna Labs Commercial
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License Agreement.
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Alternatively, this file can be distributed under the terms of the GNU General
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Public License V2 as published by the Free Software Foundation and can be
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found at http://www.gnu.org/licenses/gpl-2.0.html
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Alternatively, redistribution and use in source and binary forms, with or
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without modification, are permitted provided that the following conditions are
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met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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/**
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* @defgroup group_services Platform Services API
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* @{
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* The Platform Services API provides miscellaneous system services to HAL
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* drivers, such as:
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* - Registers read/write
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* - Assertions
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* - Memory barriers
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* - Endianness conversions
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*
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* And more.
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* @file plat_api/sample/al_hal_plat_services.h
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*
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* @brief API for Platform services provided for to HAL drivers
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*
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*
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*/
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#ifndef __PLAT_SERVICES_H__
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#define __PLAT_SERVICES_H__
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#include <machine/atomic.h>
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/endian.h>
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#include <sys/errno.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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/* Prototypes for all the bus_space structure functions */
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bs_protos(generic);
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bs_protos(generic_armv4);
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#define __UNUSED __attribute__((unused))
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/* *INDENT-OFF* */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* *INDENT-ON* */
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/*
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* WMA: This is a hack which allows not modifying the __iomem accessing HAL code.
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* On ARMv7, bus_handle holds the information about VA of accessed memory. It
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* is possible to use direct load/store instruction instead of bus_dma machinery.
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* WARNING: This is not guaranteed to stay that way forever, nor that
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* on other architectures these variables behave similarly. Keep that
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* in mind during porting to other systems.
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*/
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/**
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* Read MMIO 8 bits register
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* @param offset register offset
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*
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* @return register value
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*/
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static uint8_t al_reg_read8(uint8_t * offset);
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/**
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* Read MMIO 16 bits register
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* @param offset register offset
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*
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* @return register value
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*/
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static uint16_t al_reg_read16(uint16_t * offset);
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/**
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* Read MMIO 32 bits register
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* @param offset register offset
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*
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* @return register value
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*/
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static uint32_t al_reg_read32(uint32_t * offset);
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/**
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* Read MMIO 64 bits register
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* @param offset register offset
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*
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* @return register value
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*/
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uint64_t al_reg_read64(uint64_t * offset);
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/**
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* Relaxed read MMIO 32 bits register
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*
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* Relaxed register read/write functions don't involve cpu instructions that
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* force syncronization, nor ordering between the register access and memory
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* data access.
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* These instructions are used in performance critical code to avoid the
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* overhead of the synchronization instructions.
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*
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* @param offset register offset
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*
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* @return register value
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*/
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#define al_bus_dma_to_va(bus_tag, bus_handle) ((void*)bus_handle)
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/**
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* Relaxed read MMIO 32 bits register
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*
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* Relaxed register read/write functions don't involve cpu instructions that
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* force syncronization, nor ordering between the register access and memory
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* data access.
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* These instructions are used in performance critical code to avoid the
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* overhead of the synchronization instructions.
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*
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* @param offset register offset
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*
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* @return register value
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*/
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#define al_reg_read32_relaxed(l) generic_bs_r_4(NULL, (bus_space_handle_t)l, 0)
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/**
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* Relaxed write to MMIO 32 bits register
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*
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* Relaxed register read/write functions don't involve cpu instructions that
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* force syncronization, nor ordering between the register access and memory
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* data access.
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* These instructions are used in performance critical code to avoid the
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* overhead of the synchronization instructions.
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*
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* @param offset register offset
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* @param val value to write to the register
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*/
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#define al_reg_write32_relaxed(l,v) generic_bs_w_4(NULL, (bus_space_handle_t)l, 0, v)
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/**
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* Write to MMIO 8 bits register
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* @param offset register offset
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* @param val value to write to the register
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*/
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#define al_reg_write8(l,v) do { dsb(); generic_bs_w_1(NULL, (bus_space_handle_t)l, 0, v); dmb(); } while (0)
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/**
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* Write to MMIO 16 bits register
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* @param offset register offset
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* @param val value to write to the register
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*/
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#define al_reg_write16(l,v) do { dsb(); generic_bs_w_2(NULL, (bus_space_handle_t)l, 0, v); dmb(); } while (0)
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/**
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* Write to MMIO 32 bits register
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* @param offset register offset
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* @param val value to write to the register
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*/
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#define al_reg_write32(l,v) do { dsb(); generic_bs_w_4(NULL, (bus_space_handle_t)l, 0, v); dmb(); } while (0)
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/**
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* Write to MMIO 64 bits register
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* @param offset register offset
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* @param val value to write to the register
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*/
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#define al_reg_write64(l,v) do { dsb(); generic_bs_w_8(NULL, (bus_space_handle_t)l, 0, v); dmb(); } while (0)
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static inline uint8_t
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al_reg_read8(uint8_t *l)
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{
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dsb();
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return (generic_bs_r_1(NULL, (bus_space_handle_t)l, 0));
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}
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static inline uint16_t
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al_reg_read16(uint16_t *l)
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{
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dsb();
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return (generic_bs_r_2(NULL, (bus_space_handle_t)l, 0));
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}
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static inline uint32_t
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al_reg_read32(uint32_t *l)
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{
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dsb();
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return (generic_bs_r_4(NULL, (bus_space_handle_t)l, 0));
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}
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#define AL_DBG_LEVEL_NONE 0
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#define AL_DBG_LEVEL_ERR 1
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#define AL_DBG_LEVEL_WARN 2
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#define AL_DBG_LEVEL_INFO 3
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#define AL_DBG_LEVEL_DBG 4
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#define AL_DBG_LEVEL AL_DBG_LEVEL_ERR
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extern struct mtx al_dbg_lock;
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#define AL_DBG_LOCK() mtx_lock_spin(&al_dbg_lock)
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#define AL_DBG_UNLOCK() mtx_unlock_spin(&al_dbg_lock)
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/**
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* print message
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*
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* @param format The format string
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* @param ... Additional arguments
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*/
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#define al_print(type, fmt, ...) do { if (AL_DBG_LEVEL >= AL_DBG_LEVEL_NONE) { AL_DBG_LOCK(); printf(fmt, ##__VA_ARGS__); AL_DBG_UNLOCK(); } } while(0)
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/**
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* print error message
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*
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* @param format
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*/
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#define al_err(...) do { if (AL_DBG_LEVEL >= AL_DBG_LEVEL_ERR) { AL_DBG_LOCK(); printf(__VA_ARGS__); AL_DBG_UNLOCK(); } } while(0)
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/**
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* print warning message
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*
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* @param format
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*/
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#define al_warn(...) do { if (AL_DBG_LEVEL >= AL_DBG_LEVEL_WARN) { AL_DBG_LOCK(); printf(__VA_ARGS__); AL_DBG_UNLOCK(); } } while(0)
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/**
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* print info message
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*
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* @param format
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*/
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#define al_info(...) do { if (AL_DBG_LEVEL >= AL_DBG_LEVEL_INFO) { AL_DBG_LOCK(); printf(__VA_ARGS__); AL_DBG_UNLOCK(); } } while(0)
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/**
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* print debug message
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*
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* @param format
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*/
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#define al_dbg(...) do { if (AL_DBG_LEVEL >= AL_DBG_LEVEL_DBG) { AL_DBG_LOCK(); printf(__VA_ARGS__); AL_DBG_UNLOCK(); } } while(0)
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/**
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* Assertion
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*
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* @param condition
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*/
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#define al_assert(COND) \
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do { \
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if (!(COND)) \
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al_err( \
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"%s:%d:%s: Assertion failed! (%s)\n", \
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__FILE__, __LINE__, __func__, #COND); \
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} while(AL_FALSE)
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/**
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* Make sure data will be visible by other masters (other CPUS and DMA).
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* usually this is achieved by the ARM DMB instruction.
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*/
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static void al_data_memory_barrier(void);
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/**
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* Make sure data will be visible by DMA masters, no restriction for other cpus
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*/
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static inline void
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al_data_memory_barrier(void)
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{
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dsb();
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}
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/**
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* Make sure data will be visible in order by other cpus masters.
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*/
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static inline void
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al_smp_data_memory_barrier(void)
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{
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dsb();
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}
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/**
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* Make sure write data will be visible in order by other cpus masters.
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*/
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static inline void
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al_local_data_memory_barrier(void)
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{
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dsb();
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}
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/**
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* al_udelay - micro sec delay
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*/
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#define al_udelay(u) DELAY(u)
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/**
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* al_msleep - mili sec delay
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*/
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#define al_msleep(m) DELAY((m) * 1000)
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/**
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* swap half word to little endian
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*
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* @param x 16 bit value
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*
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* @return the value in little endian
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*/
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#define swap16_to_le(x) htole16(x)
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/**
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* swap word to little endian
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*
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* @param x 32 bit value
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*
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* @return the value in little endian
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*/
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#define swap32_to_le(x) htole32(x)
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/**
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* swap 8 bytes to little endian
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*
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* @param x 64 bit value
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*
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* @return the value in little endian
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*/
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#define swap64_to_le(x) htole64(x)
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/**
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* swap half word from little endian
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*
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* @param x 16 bit value
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*
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* @return the value in the cpu endianess
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*/
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#define swap16_from_le(x) le16toh(x)
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/**
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* swap word from little endian
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*
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* @param x 32 bit value
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*
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* @return the value in the cpu endianess
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*/
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#define swap32_from_le(x) le32toh(x)
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/**
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* swap 8 bytes from little endian
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*
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* @param x 64 bit value
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*
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* @return the value in the cpu endianess
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*/
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#define swap64_from_le(x) le64toh(x)
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/**
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* Memory set
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*
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* @param p memory pointer
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* @param val value for setting
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* @param cnt number of bytes to set
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*/
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#define al_memset(p, val, cnt) memset(p, val, cnt)
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/**
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* Memory copy
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*
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* @param p1 memory pointer
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* @param p2 memory pointer
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* @param cnt number of bytes to copy
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*/
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#define al_memcpy(p1, p2, cnt) memcpy(p1, p2, cnt)
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/**
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* Memory compare
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*
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* @param p1 memory pointer
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* @param p2 memory pointer
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* @param cnt number of bytes to compare
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*/
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#define al_memcmp(p1, p2, cnt) memcmp(p1, p2, cnt)
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/**
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* String compare
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*
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* @param s1 string pointer
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* @param s2 string pointer
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*/
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#define al_strcmp(s1, s2) strcmp(s1, s2)
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#define al_get_cpu_id() 0
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/* *INDENT-OFF* */
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#ifdef __cplusplus
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}
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#endif
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/* *INDENT-ON* */
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/** @} end of Platform Services API group */
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#endif /* __PLAT_SERVICES_H__ */
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