152 lines
5.1 KiB
C
152 lines
5.1 KiB
C
/*-
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*******************************************************************************
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Copyright (C) 2015 Annapurna Labs Ltd.
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This file may be licensed under the terms of the Annapurna Labs Commercial
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License Agreement.
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Alternatively, this file can be distributed under the terms of the GNU General
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Public License V2 as published by the Free Software Foundation and can be
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found at http://www.gnu.org/licenses/gpl-2.0.html
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Alternatively, redistribution and use in source and binary forms, with or
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without modification, are permitted provided that the following conditions are
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met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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/**
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* @{
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* @file al_hal_udma_iofic.c
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*
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* @brief unit interrupts configurations
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*
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*/
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#include "al_hal_udma_iofic.h"
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#include "al_hal_udma_regs.h"
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/*
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* configure the interrupt registers, interrupts will are kept masked
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*/
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static int al_udma_main_iofic_config(struct al_iofic_regs __iomem *base,
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enum al_iofic_mode mode)
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{
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switch (mode) {
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case AL_IOFIC_MODE_LEGACY:
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al_iofic_config(base, AL_INT_GROUP_A,
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INT_CONTROL_GRP_SET_ON_POSEDGE |
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INT_CONTROL_GRP_MASK_MSI_X |
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INT_CONTROL_GRP_CLEAR_ON_READ);
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al_iofic_config(base, AL_INT_GROUP_B,
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INT_CONTROL_GRP_CLEAR_ON_READ |
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INT_CONTROL_GRP_MASK_MSI_X);
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al_iofic_config(base, AL_INT_GROUP_C,
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INT_CONTROL_GRP_CLEAR_ON_READ |
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INT_CONTROL_GRP_MASK_MSI_X);
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al_iofic_config(base, AL_INT_GROUP_D,
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INT_CONTROL_GRP_SET_ON_POSEDGE |
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INT_CONTROL_GRP_MASK_MSI_X |
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INT_CONTROL_GRP_CLEAR_ON_READ);
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break;
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case AL_IOFIC_MODE_MSIX_PER_Q:
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al_iofic_config(base, AL_INT_GROUP_A,
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INT_CONTROL_GRP_SET_ON_POSEDGE |
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INT_CONTROL_GRP_AUTO_MASK |
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INT_CONTROL_GRP_AUTO_CLEAR);
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al_iofic_config(base, AL_INT_GROUP_B,
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INT_CONTROL_GRP_AUTO_CLEAR |
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INT_CONTROL_GRP_AUTO_MASK |
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INT_CONTROL_GRP_CLEAR_ON_READ);
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al_iofic_config(base, AL_INT_GROUP_C,
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INT_CONTROL_GRP_AUTO_CLEAR |
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INT_CONTROL_GRP_AUTO_MASK |
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INT_CONTROL_GRP_CLEAR_ON_READ);
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al_iofic_config(base, AL_INT_GROUP_D,
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INT_CONTROL_GRP_SET_ON_POSEDGE |
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INT_CONTROL_GRP_CLEAR_ON_READ |
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INT_CONTROL_GRP_MASK_MSI_X);
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break;
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case AL_IOFIC_MODE_MSIX_PER_GROUP:
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al_iofic_config(base, AL_INT_GROUP_A,
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INT_CONTROL_GRP_SET_ON_POSEDGE |
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INT_CONTROL_GRP_AUTO_CLEAR |
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INT_CONTROL_GRP_AUTO_MASK);
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al_iofic_config(base, AL_INT_GROUP_B,
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INT_CONTROL_GRP_CLEAR_ON_READ |
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INT_CONTROL_GRP_MASK_MSI_X);
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al_iofic_config(base, AL_INT_GROUP_C,
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INT_CONTROL_GRP_CLEAR_ON_READ |
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INT_CONTROL_GRP_MASK_MSI_X);
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al_iofic_config(base, AL_INT_GROUP_D,
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INT_CONTROL_GRP_SET_ON_POSEDGE |
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INT_CONTROL_GRP_CLEAR_ON_READ |
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INT_CONTROL_GRP_MASK_MSI_X);
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break;
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default:
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al_err("%s: invalid mode (%d)\n", __func__, mode);
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return -EINVAL;
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}
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al_dbg("%s: base.%p mode %d\n", __func__, base, mode);
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return 0;
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}
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/*
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* configure the UDMA interrupt registers, interrupts are kept masked
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*/
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int al_udma_iofic_config(struct unit_regs __iomem *regs, enum al_iofic_mode mode,
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uint32_t m2s_errors_disable,
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uint32_t m2s_aborts_disable,
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uint32_t s2m_errors_disable,
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uint32_t s2m_aborts_disable)
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{
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int rc;
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rc = al_udma_main_iofic_config(®s->gen.interrupt_regs.main_iofic, mode);
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if (rc != 0)
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return rc;
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al_iofic_unmask(®s->gen.interrupt_regs.secondary_iofic_ctrl, AL_INT_GROUP_A, ~m2s_errors_disable);
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al_iofic_abort_mask(®s->gen.interrupt_regs.secondary_iofic_ctrl, AL_INT_GROUP_A, m2s_aborts_disable);
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al_iofic_unmask(®s->gen.interrupt_regs.secondary_iofic_ctrl, AL_INT_GROUP_B, ~s2m_errors_disable);
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al_iofic_abort_mask(®s->gen.interrupt_regs.secondary_iofic_ctrl, AL_INT_GROUP_B, s2m_aborts_disable);
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al_dbg("%s base.%p mode %d\n", __func__, regs, mode);
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return 0;
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}
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/*
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* return the offset of the unmask register for a given group
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*/
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uint32_t __iomem * al_udma_iofic_unmask_offset_get(
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struct unit_regs __iomem *regs,
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enum al_udma_iofic_level level,
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int group)
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{
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al_assert(al_udma_iofic_level_and_group_valid(level, group));
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return al_iofic_unmask_offset_get(al_udma_iofic_reg_base_get(regs, level), group);
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}
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/** @} end of UDMA group */
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