186 lines
5.5 KiB
C
186 lines
5.5 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Inc. nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* @file
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*
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* General Purpose IO interface.
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*
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* <hr>$Revision: 70030 $<hr>
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*/
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#ifndef __CVMX_GPIO_H__
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#define __CVMX_GPIO_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* CSR typedefs have been moved to cvmx-gpio-defs.h */
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/**
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* Clear the interrupt rising edge detector for the supplied
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* pins in the mask. Chips which have more than 16 GPIO pins
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* can't use them for interrupts.
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e
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* @param clear_mask Mask of pins to clear
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*/
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static inline void cvmx_gpio_interrupt_clear(uint16_t clear_mask)
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{
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if (OCTEON_IS_MODEL(OCTEON_CN61XX))
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{
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cvmx_gpio_multi_cast_t multi_cast;
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cvmx_gpio_bit_cfgx_t gpio_bit;
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int core = cvmx_get_core_num();
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multi_cast.u64 = cvmx_read_csr(CVMX_GPIO_MULTI_CAST);
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gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(core));
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/* If Multicast mode is enabled, and GPIO interrupt is enabled for
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edge detection, then GPIO<4..7> interrupts are per core */
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if (multi_cast.s.en && gpio_bit.s.int_en && gpio_bit.s.int_type)
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{
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/* Clear GPIO<4..7> per core */
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cvmx_ciu_intx_sum0_t ciu_sum0;
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ciu_sum0.u64 = cvmx_read_csr(CVMX_CIU_INTX_SUM0(core * 2));
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ciu_sum0.s.gpio = clear_mask & 0xf0;
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cvmx_write_csr(CVMX_CIU_INTX_SUM0(core * 2), ciu_sum0.u64);
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/* Clear other GPIO pins for all cores. */
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cvmx_write_csr(CVMX_GPIO_INT_CLR, (clear_mask & ~0xf0));
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return;
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}
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}
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/* Clear GPIO pins state across all cores and common interrupt states. */
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cvmx_gpio_int_clr_t gpio_int_clr;
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gpio_int_clr.u64 = 0;
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gpio_int_clr.s.type = clear_mask;
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cvmx_write_csr(CVMX_GPIO_INT_CLR, gpio_int_clr.u64);
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}
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/**
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* GPIO Output Pin
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*
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* @param bit The GPIO to use
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* @param mode Drive GPIO as output pin or not.
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*
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*/
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static inline void cvmx_gpio_cfg(int bit, int mode)
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{
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if (bit > 15 && bit < 20)
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{
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/* CN61XX/CN66XX has 20 GPIO pins and only 16 are interruptable. */
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if (OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN66XX))
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{
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cvmx_gpio_xbit_cfgx_t gpio_xbit;
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gpio_xbit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(bit));
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if (mode)
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gpio_xbit.s.tx_oe = 1;
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else
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gpio_xbit.s.tx_oe = 0;
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cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(bit), gpio_xbit.u64);
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}
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else
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cvmx_dprintf("cvmx_gpio_cfg: Invalid GPIO bit(%d)\n", bit);
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}
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else
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{
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cvmx_gpio_bit_cfgx_t gpio_bit;
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gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(bit));
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if (mode)
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gpio_bit.s.tx_oe = 1;
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else
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gpio_bit.s.tx_oe = 0;
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cvmx_write_csr(CVMX_GPIO_BIT_CFGX(bit), gpio_bit.u64);
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}
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}
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/**
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* GPIO Read Data
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*
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* @return Status of the GPIO pins
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*/
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static inline uint32_t cvmx_gpio_read(void)
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{
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cvmx_gpio_rx_dat_t gpio_rx_dat;
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gpio_rx_dat.u64 = cvmx_read_csr(CVMX_GPIO_RX_DAT);
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return gpio_rx_dat.s.dat;
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}
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/**
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* GPIO Clear pin
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*
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* @param clear_mask Bit mask to indicate which bits to drive to '0'.
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*/
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static inline void cvmx_gpio_clear(uint32_t clear_mask)
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{
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cvmx_gpio_tx_clr_t gpio_tx_clr;
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gpio_tx_clr.u64 = 0;
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gpio_tx_clr.s.clr = clear_mask;
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cvmx_write_csr(CVMX_GPIO_TX_CLR, gpio_tx_clr.u64);
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}
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/**
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* GPIO Set pin
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*
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* @param set_mask Bit mask to indicate which bits to drive to '1'.
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*/
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static inline void cvmx_gpio_set(uint32_t set_mask)
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{
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cvmx_gpio_tx_set_t gpio_tx_set;
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gpio_tx_set.u64 = 0;
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gpio_tx_set.s.set = set_mask;
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cvmx_write_csr(CVMX_GPIO_TX_SET, gpio_tx_set.u64);
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}
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#ifdef __cplusplus
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}
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#endif
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#endif
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