542 lines
26 KiB
C
542 lines
26 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Inc. nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* cvmx-ndf-defs.h
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*
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* Configuration and status register (CSR) type definitions for
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* Octeon ndf.
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*
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* This file is auto generated. Do not edit.
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*
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* <hr>$Revision$<hr>
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*
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*/
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#ifndef __CVMX_NDF_DEFS_H__
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#define __CVMX_NDF_DEFS_H__
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_NDF_BT_PG_INFO CVMX_NDF_BT_PG_INFO_FUNC()
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static inline uint64_t CVMX_NDF_BT_PG_INFO_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
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cvmx_warn("CVMX_NDF_BT_PG_INFO not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001070001000018ull);
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}
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#else
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#define CVMX_NDF_BT_PG_INFO (CVMX_ADD_IO_SEG(0x0001070001000018ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_NDF_CMD CVMX_NDF_CMD_FUNC()
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static inline uint64_t CVMX_NDF_CMD_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
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cvmx_warn("CVMX_NDF_CMD not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001070001000000ull);
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}
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#else
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#define CVMX_NDF_CMD (CVMX_ADD_IO_SEG(0x0001070001000000ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_NDF_DRBELL CVMX_NDF_DRBELL_FUNC()
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static inline uint64_t CVMX_NDF_DRBELL_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
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cvmx_warn("CVMX_NDF_DRBELL not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001070001000030ull);
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}
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#else
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#define CVMX_NDF_DRBELL (CVMX_ADD_IO_SEG(0x0001070001000030ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_NDF_ECC_CNT CVMX_NDF_ECC_CNT_FUNC()
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static inline uint64_t CVMX_NDF_ECC_CNT_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
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cvmx_warn("CVMX_NDF_ECC_CNT not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001070001000010ull);
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}
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#else
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#define CVMX_NDF_ECC_CNT (CVMX_ADD_IO_SEG(0x0001070001000010ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_NDF_INT CVMX_NDF_INT_FUNC()
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static inline uint64_t CVMX_NDF_INT_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
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cvmx_warn("CVMX_NDF_INT not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001070001000020ull);
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}
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#else
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#define CVMX_NDF_INT (CVMX_ADD_IO_SEG(0x0001070001000020ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_NDF_INT_EN CVMX_NDF_INT_EN_FUNC()
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static inline uint64_t CVMX_NDF_INT_EN_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
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cvmx_warn("CVMX_NDF_INT_EN not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001070001000028ull);
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}
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#else
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#define CVMX_NDF_INT_EN (CVMX_ADD_IO_SEG(0x0001070001000028ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_NDF_MISC CVMX_NDF_MISC_FUNC()
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static inline uint64_t CVMX_NDF_MISC_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
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cvmx_warn("CVMX_NDF_MISC not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001070001000008ull);
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}
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#else
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#define CVMX_NDF_MISC (CVMX_ADD_IO_SEG(0x0001070001000008ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_NDF_ST_REG CVMX_NDF_ST_REG_FUNC()
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static inline uint64_t CVMX_NDF_ST_REG_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CN68XX)))
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cvmx_warn("CVMX_NDF_ST_REG not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001070001000038ull);
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}
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#else
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#define CVMX_NDF_ST_REG (CVMX_ADD_IO_SEG(0x0001070001000038ull))
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#endif
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/**
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* cvmx_ndf_bt_pg_info
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*
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* Notes:
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* NDF_BT_PG_INFO provides page size and number of column plus row address cycles information. SW writes to this CSR
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* during boot from Nand Flash. Additionally SW also writes the multiplier value for timing parameters. This value is
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* used during boot, in the SET_TM_PARAM command. This information is used only by the boot load state machine and is
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* otherwise a don't care, once boot is disabled. Also, boot dma's do not use this value.
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*
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* Bytes per Nand Flash page = 2 ** (SIZE + 1) times 256 bytes.
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* 512, 1k, 2k, 4k, 8k, 16k, 32k and 64k are legal bytes per page values
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*
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* Legal values for ADR_CYC field are 3 through 8. SW CSR writes with a value less than 3 will write a 3 to this
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* field, and a SW CSR write with a value greater than 8, will write an 8 to this field.
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*
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* Like all NDF_... registers, 64-bit operations must be used to access this register
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*/
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union cvmx_ndf_bt_pg_info {
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uint64_t u64;
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struct cvmx_ndf_bt_pg_info_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_11_63 : 53;
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uint64_t t_mult : 4; /**< Boot time TIM_MULT[3:0] field of SET__TM_PAR[63:0]
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command */
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uint64_t adr_cyc : 4; /**< # of column address cycles */
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uint64_t size : 3; /**< bytes per page in the nand device */
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#else
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uint64_t size : 3;
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uint64_t adr_cyc : 4;
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uint64_t t_mult : 4;
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uint64_t reserved_11_63 : 53;
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#endif
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} s;
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struct cvmx_ndf_bt_pg_info_s cn52xx;
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struct cvmx_ndf_bt_pg_info_s cn63xx;
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struct cvmx_ndf_bt_pg_info_s cn63xxp1;
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struct cvmx_ndf_bt_pg_info_s cn66xx;
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struct cvmx_ndf_bt_pg_info_s cn68xx;
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struct cvmx_ndf_bt_pg_info_s cn68xxp1;
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};
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typedef union cvmx_ndf_bt_pg_info cvmx_ndf_bt_pg_info_t;
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/**
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* cvmx_ndf_cmd
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*
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* Notes:
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* When SW reads this csr, RD_VAL bit in NDF_MISC csr is cleared to 0. SW must always write all 8 bytes whenever it writes
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* this csr. If there are fewer than 8 bytes left in the command sequence that SW wants the NAND flash controller to execute, it
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* must insert Idle (WAIT) commands to make up 8 bytes. SW also must ensure there is enough vacancy in the command fifo to accept these
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* 8 bytes, by first reading the FR_BYT field in the NDF_MISC csr.
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*
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* Like all NDF_... registers, 64-bit operations must be used to access this register
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*/
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union cvmx_ndf_cmd {
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uint64_t u64;
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struct cvmx_ndf_cmd_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t nf_cmd : 64; /**< 8 Command Bytes */
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#else
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uint64_t nf_cmd : 64;
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#endif
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} s;
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struct cvmx_ndf_cmd_s cn52xx;
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struct cvmx_ndf_cmd_s cn63xx;
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struct cvmx_ndf_cmd_s cn63xxp1;
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struct cvmx_ndf_cmd_s cn66xx;
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struct cvmx_ndf_cmd_s cn68xx;
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struct cvmx_ndf_cmd_s cn68xxp1;
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};
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typedef union cvmx_ndf_cmd cvmx_ndf_cmd_t;
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/**
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* cvmx_ndf_drbell
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*
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* Notes:
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* SW csr writes will increment CNT by the signed 8 bit value being written. SW csr reads return the current CNT value.
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* HW will also modify the value of the CNT field. Everytime HW executes a BUS_ACQ[15:0] command, to arbitrate and win the
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* flash bus, it decrements the CNT field by 1. If the CNT field is already 0 or negative, HW command execution unit will
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* stall when it fetches the new BUS_ACQ[15:0] command, from the command fifo. Only when the SW writes to this CSR with a
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* non-zero data value, can the execution unit come out of the stalled condition, and resume execution.
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*
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* The intended use of this doorbell CSR is to control execution of the Nand Flash commands. The NDF execution unit
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* has to arbitrate for the flash bus, before it can enable a Nand Flash device connected to the Octeon chip, by
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* asserting the device's chip enable. Therefore SW should first load the command fifo, with a full sequence of
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* commands to perform a Nand Flash device task. This command sequence will start with a bus acquire command and
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* the last command in the sequence will be a bus release command. The execution unit will start execution of
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* the sequence only if the [CNT] field is non-zero when it fetches the bus acquire command, which is the first
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* command in this sequence. SW can also, load multiple such sequences, each starting with a chip enable command
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* and ending with a chip disable command, and then write a non-zero data value to this csr to increment the
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* CNT field by the number of the command sequences, loaded to the command fifo.
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*
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* Like all NDF_... registers, 64-bit operations must be used to access this register
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*/
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union cvmx_ndf_drbell {
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uint64_t u64;
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struct cvmx_ndf_drbell_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_8_63 : 56;
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uint64_t cnt : 8; /**< Doorbell count register, 2's complement 8 bit value */
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#else
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uint64_t cnt : 8;
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uint64_t reserved_8_63 : 56;
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#endif
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} s;
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struct cvmx_ndf_drbell_s cn52xx;
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struct cvmx_ndf_drbell_s cn63xx;
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struct cvmx_ndf_drbell_s cn63xxp1;
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struct cvmx_ndf_drbell_s cn66xx;
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struct cvmx_ndf_drbell_s cn68xx;
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struct cvmx_ndf_drbell_s cn68xxp1;
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};
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typedef union cvmx_ndf_drbell cvmx_ndf_drbell_t;
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/**
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* cvmx_ndf_ecc_cnt
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*
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* Notes:
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* XOR_ECC[31:8] = [ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256] xor [ecc_258, ecc_257, ecc_256]
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* ecc_258, ecc_257 and ecc_256 are bytes stored in Nand Flash and read out during boot
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* ecc_gen_byt258, ecc_gen_byt257, ecc_gen_byt256 are generated from data read out from Nand Flash
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*
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* Like all NDF_... registers, 64-bit operations must be used to access this register
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*/
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union cvmx_ndf_ecc_cnt {
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uint64_t u64;
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struct cvmx_ndf_ecc_cnt_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_32_63 : 32;
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uint64_t xor_ecc : 24; /**< result of XOR of ecc read bytes and ecc genarated
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bytes. The value pertains to the last 1 bit ecc err */
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uint64_t ecc_err : 8; /**< Count = \# of 1 bit errors fixed during boot
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This count saturates instead of wrapping around. */
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#else
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uint64_t ecc_err : 8;
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uint64_t xor_ecc : 24;
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uint64_t reserved_32_63 : 32;
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#endif
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} s;
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struct cvmx_ndf_ecc_cnt_s cn52xx;
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struct cvmx_ndf_ecc_cnt_s cn63xx;
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struct cvmx_ndf_ecc_cnt_s cn63xxp1;
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struct cvmx_ndf_ecc_cnt_s cn66xx;
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struct cvmx_ndf_ecc_cnt_s cn68xx;
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struct cvmx_ndf_ecc_cnt_s cn68xxp1;
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};
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typedef union cvmx_ndf_ecc_cnt cvmx_ndf_ecc_cnt_t;
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/**
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* cvmx_ndf_int
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*
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* Notes:
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* FULL status is updated when the command fifo becomes full as a result of SW writing a new command to it.
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*
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* EMPTY status is updated when the command fifo becomes empty as a result of command execution unit fetching the
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* last instruction out of the command fifo.
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*
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* Like all NDF_... registers, 64-bit operations must be used to access this register
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*/
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union cvmx_ndf_int {
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uint64_t u64;
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struct cvmx_ndf_int_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_7_63 : 57;
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uint64_t ovrf : 1; /**< NDF_CMD write when fifo is full. Generally a
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fatal error. */
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uint64_t ecc_mult : 1; /**< Multi bit ECC error detected during boot */
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uint64_t ecc_1bit : 1; /**< Single bit ECC error detected and fixed during boot */
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uint64_t sm_bad : 1; /**< One of the state machines in a bad state */
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uint64_t wdog : 1; /**< Watch Dog timer expired during command execution */
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uint64_t full : 1; /**< Command fifo is full */
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uint64_t empty : 1; /**< Command fifo is empty */
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#else
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uint64_t empty : 1;
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uint64_t full : 1;
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uint64_t wdog : 1;
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uint64_t sm_bad : 1;
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uint64_t ecc_1bit : 1;
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uint64_t ecc_mult : 1;
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uint64_t ovrf : 1;
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uint64_t reserved_7_63 : 57;
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#endif
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} s;
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struct cvmx_ndf_int_s cn52xx;
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struct cvmx_ndf_int_s cn63xx;
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struct cvmx_ndf_int_s cn63xxp1;
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struct cvmx_ndf_int_s cn66xx;
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struct cvmx_ndf_int_s cn68xx;
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struct cvmx_ndf_int_s cn68xxp1;
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};
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typedef union cvmx_ndf_int cvmx_ndf_int_t;
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/**
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* cvmx_ndf_int_en
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*
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* Notes:
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* Like all NDF_... registers, 64-bit operations must be used to access this register
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*
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*/
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union cvmx_ndf_int_en {
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uint64_t u64;
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struct cvmx_ndf_int_en_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_7_63 : 57;
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uint64_t ovrf : 1; /**< Wrote to a full command fifo */
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uint64_t ecc_mult : 1; /**< Multi bit ECC error detected during boot */
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uint64_t ecc_1bit : 1; /**< Single bit ECC error detected and fixed during boot */
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uint64_t sm_bad : 1; /**< One of the state machines in a bad state */
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uint64_t wdog : 1; /**< Watch Dog timer expired during command execution */
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uint64_t full : 1; /**< Command fifo is full */
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uint64_t empty : 1; /**< Command fifo is empty */
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#else
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uint64_t empty : 1;
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uint64_t full : 1;
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uint64_t wdog : 1;
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uint64_t sm_bad : 1;
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uint64_t ecc_1bit : 1;
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uint64_t ecc_mult : 1;
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uint64_t ovrf : 1;
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uint64_t reserved_7_63 : 57;
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#endif
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} s;
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struct cvmx_ndf_int_en_s cn52xx;
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struct cvmx_ndf_int_en_s cn63xx;
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struct cvmx_ndf_int_en_s cn63xxp1;
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struct cvmx_ndf_int_en_s cn66xx;
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struct cvmx_ndf_int_en_s cn68xx;
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struct cvmx_ndf_int_en_s cn68xxp1;
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};
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typedef union cvmx_ndf_int_en cvmx_ndf_int_en_t;
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/**
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* cvmx_ndf_misc
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*
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* Notes:
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* NBR_HWM this field specifies the high water mark for the NCB outbound load/store commands receive fifo.
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* the fifo size is 16 entries.
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*
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* WAIT_CNT this field allows glitch filtering of the WAIT_n input to octeon, from Flash Memory. The count
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* represents number of eclk cycles.
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*
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* FR_BYT this field specifies \# of unfilled bytes in the command fifo. Bytes become unfilled as commands
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* complete execution and exit. (fifo is 256 bytes when BT_DIS=0, and 1536 bytes when BT_DIS=1)
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*
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* RD_DONE this W1C bit is set to 1 by HW when it reads the last 8 bytes out of the command fifo,
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* in response to RD_CMD bit being set to 1 by SW.
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*
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* RD_VAL this read only bit is set to 1 by HW when it reads next 8 bytes from command fifo in response
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* to RD_CMD bit being set to 1. A SW read of NDF_CMD csr clears this bit to 0.
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*
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* RD_CMD this R/W bit starts read out from the command fifo, 8 bytes at a time. SW should first read the
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* RD_VAL bit in this csr to see if next 8 bytes from the command fifo are available in the
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* NDF_CMD csr. All command fifo reads start and end on an 8 byte boundary. A RD_CMD in the
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* middle of command execution will cause the execution to freeze until RD_DONE is set to 1. RD_CMD
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* bit will be cleared on any NDF_CMD csr write by SW.
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*
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* BT_DMA this indicates to the NAND flash boot control state machine that boot dma read can begin.
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* SW should set this bit to 1 after SW has loaded the command fifo. HW sets the bit to 0
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* when boot dma command execution is complete. If chip enable 0 is not nand flash, this bit is
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* permanently 1'b0 with SW writes ignored. Whenever BT_DIS=1, this bit will be 0.
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*
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* BT_DIS this R/W bit indicates to NAND flash boot control state machine that boot operation has ended.
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* whenever this bit changes from 0 to a 1, the command fifo is emptied as a side effect. This bit must
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* never be set when booting from nand flash and region zero is enabled.
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*
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* EX_DIS When 1, command execution stops after completing execution of all commands currently in the command
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* fifo. Once command execution has stopped, and then new commands are loaded into the command fifo, execution
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* will not resume as long as this bit is 1. When this bit is 0, command execution will resume if command fifo
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* is not empty. EX_DIS should be set to 1, during boot i.e. when BT_DIS = 0.
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*
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* RST_FF reset command fifo to make it empty, any command inflight is not aborted before reseting
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* the fifo. The fifo comes up empty at the end of power on reset.
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*
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* Like all NDF_... registers, 64-bit operations must be used to access this register
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*/
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union cvmx_ndf_misc {
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uint64_t u64;
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struct cvmx_ndf_misc_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_28_63 : 36;
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uint64_t mb_dis : 1; /**< Disable multibit error hangs and allow boot loads
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or boot dma's proceed as if no multi bit errors
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occured. HW will fix single bit errors as usual */
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uint64_t nbr_hwm : 3; /**< Hi Water mark for NBR fifo or load/stores */
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uint64_t wait_cnt : 6; /**< WAIT input filter count */
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uint64_t fr_byt : 11; /**< Number of unfilled Command fifo bytes */
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uint64_t rd_done : 1; /**< This W1C bit is set to 1 by HW when it completes
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command fifo read out, in response to RD_CMD */
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uint64_t rd_val : 1; /**< This RO bit is set to 1 by HW when it reads next 8
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bytes from Command fifo into the NDF_CMD csr
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SW reads NDF_CMD csr, HW clears this bit to 0 */
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uint64_t rd_cmd : 1; /**< When 1, HW reads out contents of the Command fifo 8
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bytes at a time into the NDF_CMD csr */
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uint64_t bt_dma : 1; /**< When set to 1, boot time dma is enabled */
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uint64_t bt_dis : 1; /**< When boot operation is over SW must set to 1
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causes boot state mchines to sleep */
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uint64_t ex_dis : 1; /**< When set to 1, suspends execution of commands at
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next command in the fifo. */
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uint64_t rst_ff : 1; /**< 1=reset command fifo to make it empty,
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0=normal operation */
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#else
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uint64_t rst_ff : 1;
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uint64_t ex_dis : 1;
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uint64_t bt_dis : 1;
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uint64_t bt_dma : 1;
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uint64_t rd_cmd : 1;
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uint64_t rd_val : 1;
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uint64_t rd_done : 1;
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uint64_t fr_byt : 11;
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uint64_t wait_cnt : 6;
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uint64_t nbr_hwm : 3;
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uint64_t mb_dis : 1;
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uint64_t reserved_28_63 : 36;
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#endif
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} s;
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struct cvmx_ndf_misc_cn52xx {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_27_63 : 37;
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uint64_t nbr_hwm : 3; /**< Hi Water mark for NBR fifo or load/stores */
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uint64_t wait_cnt : 6; /**< WAIT input filter count */
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uint64_t fr_byt : 11; /**< Number of unfilled Command fifo bytes */
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uint64_t rd_done : 1; /**< This W1C bit is set to 1 by HW when it completes
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command fifo read out, in response to RD_CMD */
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uint64_t rd_val : 1; /**< This RO bit is set to 1 by HW when it reads next 8
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bytes from Command fifo into the NDF_CMD csr
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SW reads NDF_CMD csr, HW clears this bit to 0 */
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uint64_t rd_cmd : 1; /**< When 1, HW reads out contents of the Command fifo 8
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bytes at a time into the NDF_CMD csr */
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uint64_t bt_dma : 1; /**< When set to 1, boot time dma is enabled */
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uint64_t bt_dis : 1; /**< When boot operation is over SW must set to 1
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causes boot state mchines to sleep */
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uint64_t ex_dis : 1; /**< When set to 1, suspends execution of commands at
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next command in the fifo. */
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uint64_t rst_ff : 1; /**< 1=reset command fifo to make it empty,
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0=normal operation */
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#else
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uint64_t rst_ff : 1;
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uint64_t ex_dis : 1;
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uint64_t bt_dis : 1;
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uint64_t bt_dma : 1;
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uint64_t rd_cmd : 1;
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uint64_t rd_val : 1;
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uint64_t rd_done : 1;
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uint64_t fr_byt : 11;
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uint64_t wait_cnt : 6;
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uint64_t nbr_hwm : 3;
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uint64_t reserved_27_63 : 37;
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#endif
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} cn52xx;
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struct cvmx_ndf_misc_s cn63xx;
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struct cvmx_ndf_misc_s cn63xxp1;
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struct cvmx_ndf_misc_s cn66xx;
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struct cvmx_ndf_misc_s cn68xx;
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struct cvmx_ndf_misc_s cn68xxp1;
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};
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typedef union cvmx_ndf_misc cvmx_ndf_misc_t;
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/**
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* cvmx_ndf_st_reg
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*
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* Notes:
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* This CSR aggregates all state machines used in nand flash controller for debug.
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* Like all NDF_... registers, 64-bit operations must be used to access this register
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*/
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union cvmx_ndf_st_reg {
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uint64_t u64;
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struct cvmx_ndf_st_reg_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_16_63 : 48;
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uint64_t exe_idle : 1; /**< Command Execution status 1=IDLE, 0=Busy
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1 means execution of command sequence is complete
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and command fifo is empty */
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uint64_t exe_sm : 4; /**< Command Execution State machine states */
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uint64_t bt_sm : 4; /**< Boot load and Boot dma State machine states */
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uint64_t rd_ff_bad : 1; /**< CMD fifo read back State machine in bad state */
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uint64_t rd_ff : 2; /**< CMD fifo read back State machine states */
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uint64_t main_bad : 1; /**< Main State machine in bad state */
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uint64_t main_sm : 3; /**< Main State machine states */
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#else
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uint64_t main_sm : 3;
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uint64_t main_bad : 1;
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uint64_t rd_ff : 2;
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uint64_t rd_ff_bad : 1;
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uint64_t bt_sm : 4;
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uint64_t exe_sm : 4;
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uint64_t exe_idle : 1;
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uint64_t reserved_16_63 : 48;
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#endif
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} s;
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struct cvmx_ndf_st_reg_s cn52xx;
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struct cvmx_ndf_st_reg_s cn63xx;
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struct cvmx_ndf_st_reg_s cn63xxp1;
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struct cvmx_ndf_st_reg_s cn66xx;
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struct cvmx_ndf_st_reg_s cn68xx;
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struct cvmx_ndf_st_reg_s cn68xxp1;
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};
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typedef union cvmx_ndf_st_reg cvmx_ndf_st_reg_t;
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#endif
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