741 lines
23 KiB
C
741 lines
23 KiB
C
/***********************license start***************
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* Copyright (c) 2011 Cavium Inc. (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Inc. nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* @file
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*
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* Helper utilities for qlm.
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*
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* <hr>$Revision: 70129 $<hr>
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*/
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#ifdef CVMX_BUILD_FOR_LINUX_KERNEL
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#include <asm/octeon/cvmx.h>
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#include <asm/octeon/cvmx-bootmem.h>
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#include <asm/octeon/cvmx-helper-jtag.h>
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#include <asm/octeon/cvmx-qlm.h>
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#include <asm/octeon/cvmx-gmxx-defs.h>
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#include <asm/octeon/cvmx-sriox-defs.h>
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#include <asm/octeon/cvmx-sriomaintx-defs.h>
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#include <asm/octeon/cvmx-pciercx-defs.h>
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#else
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#if !defined(__FreeBSD__) || !defined(_KERNEL)
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#include "executive-config.h"
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#include "cvmx-config.h"
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#include "cvmx.h"
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#include "cvmx-bootmem.h"
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#include "cvmx-helper-jtag.h"
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#include "cvmx-qlm.h"
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#else
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#include "cvmx.h"
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#include "cvmx-bootmem.h"
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#include "cvmx-helper-jtag.h"
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#include "cvmx-qlm.h"
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#endif
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#endif
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/**
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* The JTAG chain for CN52XX and CN56XX is 4 * 268 bits long, or 1072.
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* CN5XXX full chain shift is:
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* new data => lane 3 => lane 2 => lane 1 => lane 0 => data out
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* The JTAG chain for CN63XX is 4 * 300 bits long, or 1200.
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* The JTAG chain for CN68XX is 4 * 304 bits long, or 1216.
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* The JTAG chain for CN66XX/CN61XX/CNF71XX is 4 * 304 bits long, or 1216.
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* CN6XXX full chain shift is:
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* new data => lane 0 => lane 1 => lane 2 => lane 3 => data out
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* Shift LSB first, get LSB out
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*/
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extern const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn52xx[];
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extern const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn56xx[];
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extern const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn63xx[];
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extern const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn66xx[];
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extern const __cvmx_qlm_jtag_field_t __cvmx_qlm_jtag_field_cn68xx[];
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#define CVMX_QLM_JTAG_UINT32 40
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#ifdef CVMX_BUILD_FOR_LINUX_HOST
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extern void octeon_remote_read_mem(void *buffer, uint64_t physical_address, int length);
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extern void octeon_remote_write_mem(uint64_t physical_address, const void *buffer, int length);
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uint32_t __cvmx_qlm_jtag_xor_ref[5][CVMX_QLM_JTAG_UINT32];
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#else
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typedef uint32_t qlm_jtag_uint32_t[CVMX_QLM_JTAG_UINT32];
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CVMX_SHARED qlm_jtag_uint32_t *__cvmx_qlm_jtag_xor_ref;
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#endif
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/**
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* Return the number of QLMs supported by the chip
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*
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* @return Number of QLMs
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*/
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int cvmx_qlm_get_num(void)
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{
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if (OCTEON_IS_MODEL(OCTEON_CN68XX))
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return 5;
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else if (OCTEON_IS_MODEL(OCTEON_CN66XX))
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return 3;
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else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
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return 3;
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else if (OCTEON_IS_MODEL(OCTEON_CN61XX))
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return 3;
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else if (OCTEON_IS_MODEL(OCTEON_CN56XX))
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return 4;
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else if (OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))
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return 2;
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//cvmx_dprintf("Warning: cvmx_qlm_get_num: This chip does not have QLMs\n");
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return 0;
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}
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/**
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* Return the qlm number based on the interface
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*
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* @param interface Interface to look up
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*/
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int cvmx_qlm_interface(int interface)
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{
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if (OCTEON_IS_MODEL(OCTEON_CN61XX)) {
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return (interface == 0) ? 2 : 0;
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} else if (OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX)) {
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return 2 - interface;
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} else {
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/* Must be cn68XX */
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switch(interface) {
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case 1:
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return 0;
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default:
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return interface;
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}
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}
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}
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/**
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* Return number of lanes for a given qlm
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*
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* @return Number of lanes
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*/
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int cvmx_qlm_get_lanes(int qlm)
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{
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if (OCTEON_IS_MODEL(OCTEON_CN61XX) && qlm == 1)
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return 2;
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else if (OCTEON_IS_MODEL(OCTEON_CNF71XX))
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return 2;
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return 4;
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}
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/**
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* Get the QLM JTAG fields based on Octeon model on the supported chips.
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*
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* @return qlm_jtag_field_t structure
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*/
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const __cvmx_qlm_jtag_field_t *cvmx_qlm_jtag_get_field(void)
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{
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/* Figure out which JTAG chain description we're using */
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if (OCTEON_IS_MODEL(OCTEON_CN68XX))
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return __cvmx_qlm_jtag_field_cn68xx;
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else if (OCTEON_IS_MODEL(OCTEON_CN66XX)
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|| OCTEON_IS_MODEL(OCTEON_CN61XX)
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|| OCTEON_IS_MODEL(OCTEON_CNF71XX))
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return __cvmx_qlm_jtag_field_cn66xx;
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else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
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return __cvmx_qlm_jtag_field_cn63xx;
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else if (OCTEON_IS_MODEL(OCTEON_CN56XX))
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return __cvmx_qlm_jtag_field_cn56xx;
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else if (OCTEON_IS_MODEL(OCTEON_CN52XX))
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return __cvmx_qlm_jtag_field_cn52xx;
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else
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{
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//cvmx_dprintf("cvmx_qlm_jtag_get_field: Needs update for this chip\n");
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return NULL;
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}
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}
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/**
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* Get the QLM JTAG length by going through qlm_jtag_field for each
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* Octeon model that is supported
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*
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* @return return the length.
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*/
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int cvmx_qlm_jtag_get_length(void)
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{
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const __cvmx_qlm_jtag_field_t *qlm_ptr = cvmx_qlm_jtag_get_field();
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int length = 0;
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/* Figure out how many bits are in the JTAG chain */
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while (qlm_ptr != NULL && qlm_ptr->name)
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{
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if (qlm_ptr->stop_bit > length)
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length = qlm_ptr->stop_bit + 1;
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qlm_ptr++;
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}
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return length;
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}
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/**
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* Initialize the QLM layer
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*/
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void cvmx_qlm_init(void)
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{
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int qlm;
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int qlm_jtag_length;
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char *qlm_jtag_name = "cvmx_qlm_jtag";
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int qlm_jtag_size = CVMX_QLM_JTAG_UINT32 * 8 * 4;
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static uint64_t qlm_base = 0;
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const cvmx_bootmem_named_block_desc_t *desc;
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#ifndef CVMX_BUILD_FOR_LINUX_HOST
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/* Skip actual JTAG accesses on simulator */
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if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
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return;
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#endif
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qlm_jtag_length = cvmx_qlm_jtag_get_length();
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if (4 * qlm_jtag_length > (int)sizeof(__cvmx_qlm_jtag_xor_ref[0]) * 8)
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{
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cvmx_dprintf("ERROR: cvmx_qlm_init: JTAG chain larger than XOR ref size\n");
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return;
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}
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/* No need to initialize the initial JTAG state if cvmx_qlm_jtag
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named block is already created. */
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if ((desc = cvmx_bootmem_find_named_block(qlm_jtag_name)) != NULL)
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{
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#ifdef CVMX_BUILD_FOR_LINUX_HOST
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char buffer[qlm_jtag_size];
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octeon_remote_read_mem(buffer, desc->base_addr, qlm_jtag_size);
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memcpy(__cvmx_qlm_jtag_xor_ref, buffer, qlm_jtag_size);
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#else
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__cvmx_qlm_jtag_xor_ref = cvmx_phys_to_ptr(desc->base_addr);
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#endif
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/* Initialize the internal JTAG */
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cvmx_helper_qlm_jtag_init();
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return;
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}
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/* Create named block to store the initial JTAG state. */
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qlm_base = cvmx_bootmem_phy_named_block_alloc(qlm_jtag_size, 0, 0, 128, qlm_jtag_name, CVMX_BOOTMEM_FLAG_END_ALLOC);
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if (qlm_base == -1ull)
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{
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cvmx_dprintf("ERROR: cvmx_qlm_init: Error in creating %s named block\n", qlm_jtag_name);
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return;
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}
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#ifndef CVMX_BUILD_FOR_LINUX_HOST
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__cvmx_qlm_jtag_xor_ref = cvmx_phys_to_ptr(qlm_base);
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#endif
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memset(__cvmx_qlm_jtag_xor_ref, 0, qlm_jtag_size);
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/* Initialize the internal JTAG */
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cvmx_helper_qlm_jtag_init();
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/* Read the XOR defaults for the JTAG chain */
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for (qlm=0; qlm<cvmx_qlm_get_num(); qlm++)
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{
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int i;
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/* Capture the reset defaults */
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cvmx_helper_qlm_jtag_capture(qlm);
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/* Save the reset defaults. This will shift out too much data, but
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the extra zeros don't hurt anything */
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for (i=0; i<CVMX_QLM_JTAG_UINT32; i++)
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__cvmx_qlm_jtag_xor_ref[qlm][i] = cvmx_helper_qlm_jtag_shift(qlm, 32, 0);
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}
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#ifdef CVMX_BUILD_FOR_LINUX_HOST
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/* Update the initial state for oct-remote utils. */
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{
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char buffer[qlm_jtag_size];
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memcpy(buffer, &__cvmx_qlm_jtag_xor_ref, qlm_jtag_size);
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octeon_remote_write_mem(qlm_base, buffer, qlm_jtag_size);
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}
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#endif
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/* Apply speed tweak as a workaround for errata G-16094. */
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__cvmx_qlm_speed_tweak();
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__cvmx_qlm_pcie_idle_dac_tweak();
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}
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/**
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* Lookup the bit information for a JTAG field name
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*
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* @param name Name to lookup
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*
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* @return Field info, or NULL on failure
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*/
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static const __cvmx_qlm_jtag_field_t *__cvmx_qlm_lookup_field(const char *name)
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{
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const __cvmx_qlm_jtag_field_t *ptr = cvmx_qlm_jtag_get_field();
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while (ptr->name)
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{
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if (strcmp(name, ptr->name) == 0)
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return ptr;
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ptr++;
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}
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cvmx_dprintf("__cvmx_qlm_lookup_field: Illegal field name %s\n", name);
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return NULL;
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}
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/**
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* Get a field in a QLM JTAG chain
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*
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* @param qlm QLM to get
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* @param lane Lane in QLM to get
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* @param name String name of field
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*
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* @return JTAG field value
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*/
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uint64_t cvmx_qlm_jtag_get(int qlm, int lane, const char *name)
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{
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const __cvmx_qlm_jtag_field_t *field = __cvmx_qlm_lookup_field(name);
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int qlm_jtag_length = cvmx_qlm_jtag_get_length();
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int num_lanes = cvmx_qlm_get_lanes(qlm);
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if (!field)
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return 0;
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/* Capture the current settings */
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cvmx_helper_qlm_jtag_capture(qlm);
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/* Shift past lanes we don't care about. CN6XXX shifts lane 3 first */
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cvmx_helper_qlm_jtag_shift_zeros(qlm, qlm_jtag_length * (num_lanes-1-lane)); /* Shift to the start of the field */
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cvmx_helper_qlm_jtag_shift_zeros(qlm, field->start_bit);
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/* Shift out the value and return it */
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return cvmx_helper_qlm_jtag_shift(qlm, field->stop_bit - field->start_bit + 1, 0);
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}
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/**
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* Set a field in a QLM JTAG chain
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*
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* @param qlm QLM to set
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* @param lane Lane in QLM to set, or -1 for all lanes
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* @param name String name of field
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* @param value Value of the field
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*/
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void cvmx_qlm_jtag_set(int qlm, int lane, const char *name, uint64_t value)
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{
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int i, l;
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uint32_t shift_values[CVMX_QLM_JTAG_UINT32];
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int num_lanes = cvmx_qlm_get_lanes(qlm);
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const __cvmx_qlm_jtag_field_t *field = __cvmx_qlm_lookup_field(name);
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int qlm_jtag_length = cvmx_qlm_jtag_get_length();
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int total_length = qlm_jtag_length * num_lanes;
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int bits = 0;
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if (!field)
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return;
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/* Get the current state */
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cvmx_helper_qlm_jtag_capture(qlm);
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for (i=0; i<CVMX_QLM_JTAG_UINT32; i++)
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shift_values[i] = cvmx_helper_qlm_jtag_shift(qlm, 32, 0);
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/* Put new data in our local array */
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for (l=0; l<num_lanes; l++)
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{
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uint64_t new_value = value;
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int bits;
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if ((l != lane) && (lane != -1))
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continue;
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for (bits = field->start_bit + (num_lanes-1-l)*qlm_jtag_length;
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bits <= field->stop_bit + (num_lanes-1-l)*qlm_jtag_length;
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bits++)
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{
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if (new_value & 1)
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shift_values[bits/32] |= 1<<(bits&31);
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else
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shift_values[bits/32] &= ~(1<<(bits&31));
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new_value>>=1;
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}
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}
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/* Shift out data and xor with reference */
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while (bits < total_length)
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{
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uint32_t shift = shift_values[bits/32] ^ __cvmx_qlm_jtag_xor_ref[qlm][bits/32];
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int width = total_length - bits;
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if (width > 32)
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width = 32;
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cvmx_helper_qlm_jtag_shift(qlm, width, shift);
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bits += 32;
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}
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/* Update the new data */
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cvmx_helper_qlm_jtag_update(qlm);
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/* Always give the QLM 1ms to settle after every update. This may not
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always be needed, but some of the options make significant
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electrical changes */
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cvmx_wait_usec(1000);
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}
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/**
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* Errata G-16094: QLM Gen2 Equalizer Default Setting Change.
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* CN68XX pass 1.x and CN66XX pass 1.x QLM tweak. This function tweaks the
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* JTAG setting for a QLMs to run better at 5 and 6.25Ghz.
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*/
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void __cvmx_qlm_speed_tweak(void)
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{
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cvmx_mio_qlmx_cfg_t qlm_cfg;
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int num_qlms = 0;
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int qlm;
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if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X))
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num_qlms = 5;
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else if (OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_X))
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num_qlms = 3;
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else
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return;
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/* Loop through the QLMs */
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for (qlm = 0; qlm < num_qlms; qlm++)
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{
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/* Read the QLM speed */
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qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
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/* If the QLM is at 6.25Ghz or 5Ghz then program JTAG */
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if ((qlm_cfg.s.qlm_spd == 5) || (qlm_cfg.s.qlm_spd == 12) ||
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(qlm_cfg.s.qlm_spd == 0) || (qlm_cfg.s.qlm_spd == 6) ||
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(qlm_cfg.s.qlm_spd == 11))
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{
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cvmx_qlm_jtag_set(qlm, -1, "rx_cap_gen2", 0x1);
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cvmx_qlm_jtag_set(qlm, -1, "rx_eq_gen2", 0x8);
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}
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}
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}
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/**
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* Errata G-16174: QLM Gen2 PCIe IDLE DAC change.
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* CN68XX pass 1.x, CN66XX pass 1.x and CN63XX pass 1.0-2.2 QLM tweak.
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* This function tweaks the JTAG setting for a QLMs for PCIe to run better.
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*/
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void __cvmx_qlm_pcie_idle_dac_tweak(void)
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{
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int num_qlms = 0;
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int qlm;
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if (OCTEON_IS_MODEL(OCTEON_CN68XX_PASS1_X))
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num_qlms = 5;
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else if (OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_X))
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num_qlms = 3;
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else if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X) ||
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OCTEON_IS_MODEL(OCTEON_CN63XX_PASS2_X))
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num_qlms = 3;
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else
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return;
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/* Loop through the QLMs */
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for (qlm = 0; qlm < num_qlms; qlm++)
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cvmx_qlm_jtag_set(qlm, -1, "idle_dac", 0x2);
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}
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#ifndef CVMX_BUILD_FOR_LINUX_HOST
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/**
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* Get the speed (Gbaud) of the QLM in Mhz.
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*
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* @param qlm QLM to examine
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*
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* @return Speed in Mhz
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*/
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int cvmx_qlm_get_gbaud_mhz(int qlm)
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{
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if (OCTEON_IS_MODEL(OCTEON_CN63XX))
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{
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if (qlm == 2)
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{
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cvmx_gmxx_inf_mode_t inf_mode;
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inf_mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(0));
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switch (inf_mode.s.speed)
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{
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case 0: return 5000; /* 5 Gbaud */
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case 1: return 2500; /* 2.5 Gbaud */
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case 2: return 2500; /* 2.5 Gbaud */
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case 3: return 1250; /* 1.25 Gbaud */
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case 4: return 1250; /* 1.25 Gbaud */
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case 5: return 6250; /* 6.25 Gbaud */
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case 6: return 5000; /* 5 Gbaud */
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case 7: return 2500; /* 2.5 Gbaud */
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case 8: return 3125; /* 3.125 Gbaud */
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case 9: return 2500; /* 2.5 Gbaud */
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case 10: return 1250; /* 1.25 Gbaud */
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case 11: return 5000; /* 5 Gbaud */
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case 12: return 6250; /* 6.25 Gbaud */
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case 13: return 3750; /* 3.75 Gbaud */
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case 14: return 3125; /* 3.125 Gbaud */
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default: return 0; /* Disabled */
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}
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}
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else
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{
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cvmx_sriox_status_reg_t status_reg;
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status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(qlm));
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if (status_reg.s.srio)
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{
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cvmx_sriomaintx_port_0_ctl2_t sriomaintx_port_0_ctl2;
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sriomaintx_port_0_ctl2.u32 = cvmx_read_csr(CVMX_SRIOMAINTX_PORT_0_CTL2(qlm));
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switch (sriomaintx_port_0_ctl2.s.sel_baud)
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{
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case 1: return 1250; /* 1.25 Gbaud */
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case 2: return 2500; /* 2.5 Gbaud */
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case 3: return 3125; /* 3.125 Gbaud */
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case 4: return 5000; /* 5 Gbaud */
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case 5: return 6250; /* 6.250 Gbaud */
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default: return 0; /* Disabled */
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}
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}
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else
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{
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cvmx_pciercx_cfg032_t pciercx_cfg032;
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pciercx_cfg032.u32 = cvmx_read_csr(CVMX_PCIERCX_CFG032(qlm));
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switch (pciercx_cfg032.s.ls)
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{
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case 1:
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return 2500;
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case 2:
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return 5000;
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case 4:
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return 8000;
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default:
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{
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cvmx_mio_rst_boot_t mio_rst_boot;
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mio_rst_boot.u64 = cvmx_read_csr(CVMX_MIO_RST_BOOT);
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if ((qlm == 0) && mio_rst_boot.s.qlm0_spd == 0xf)
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return 0;
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if ((qlm == 1) && mio_rst_boot.s.qlm1_spd == 0xf)
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return 0;
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return 5000; /* Best guess I can make */
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}
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}
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}
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}
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}
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else if (OCTEON_IS_MODEL(OCTEON_CN6XXX) || OCTEON_IS_MODEL(OCTEON_CNF71XX))
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{
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cvmx_mio_qlmx_cfg_t qlm_cfg;
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qlm_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
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switch (qlm_cfg.s.qlm_spd)
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{
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case 0: return 5000; /* 5 Gbaud */
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case 1: return 2500; /* 2.5 Gbaud */
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case 2: return 2500; /* 2.5 Gbaud */
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case 3: return 1250; /* 1.25 Gbaud */
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case 4: return 1250; /* 1.25 Gbaud */
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case 5: return 6250; /* 6.25 Gbaud */
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case 6: return 5000; /* 5 Gbaud */
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case 7: return 2500; /* 2.5 Gbaud */
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case 8: return 3125; /* 3.125 Gbaud */
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case 9: return 2500; /* 2.5 Gbaud */
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case 10: return 1250; /* 1.25 Gbaud */
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case 11: return 5000; /* 5 Gbaud */
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case 12: return 6250; /* 6.25 Gbaud */
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case 13: return 3750; /* 3.75 Gbaud */
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case 14: return 3125; /* 3.125 Gbaud */
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default: return 0; /* Disabled */
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}
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}
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return 0;
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}
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#endif
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/*
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* Read QLM and return status based on CN66XX.
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* @return Return 1 if QLM is SGMII
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* 2 if QLM is XAUI
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* 3 if QLM is PCIe gen2 / gen1
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* 4 if QLM is SRIO 1x4 short / long
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* 5 if QLM is SRIO 2x2 short / long
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* 6 if QLM is SRIO 4x1 short / long
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* 7 if QLM is PCIe 1x2 gen2 / gen1
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* 8 if QLM is PCIe 2x1 gen2 / gen1
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* 9 if QLM is ILK
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* 10 if QLM is RXAUI
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* -1 otherwise
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*/
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int cvmx_qlm_get_status(int qlm)
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{
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cvmx_mio_qlmx_cfg_t qlmx_cfg;
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if (OCTEON_IS_MODEL(OCTEON_CN68XX))
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{
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qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
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/* QLM is disabled when QLM SPD is 15. */
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if (qlmx_cfg.s.qlm_spd == 15)
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return -1;
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switch (qlmx_cfg.s.qlm_cfg)
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{
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case 0: /* PCIE */
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return 3;
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case 1: /* ILK */
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return 9;
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case 2: /* SGMII */
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return 1;
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case 3: /* XAUI */
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return 2;
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case 7: /* RXAUI */
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return 10;
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default: return -1;
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}
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}
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else if (OCTEON_IS_MODEL(OCTEON_CN66XX))
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{
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qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
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/* QLM is disabled when QLM SPD is 15. */
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if (qlmx_cfg.s.qlm_spd == 15)
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return -1;
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switch (qlmx_cfg.s.qlm_cfg)
|
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{
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case 0x9: /* SGMII */
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return 1;
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case 0xb: /* XAUI */
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return 2;
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case 0x0: /* PCIE gen2 */
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case 0x8: /* PCIE gen2 (alias) */
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case 0x2: /* PCIE gen1 */
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case 0xa: /* PCIE gen1 (alias) */
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|
return 3;
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|
case 0x1: /* SRIO 1x4 short */
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case 0x3: /* SRIO 1x4 long */
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|
return 4;
|
|
case 0x4: /* SRIO 2x2 short */
|
|
case 0x6: /* SRIO 2x2 long */
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|
return 5;
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|
case 0x5: /* SRIO 4x1 short */
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|
case 0x7: /* SRIO 4x1 long */
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|
if (!OCTEON_IS_MODEL(OCTEON_CN66XX_PASS1_0))
|
|
return 6;
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default:
|
|
return -1;
|
|
}
|
|
}
|
|
else if (OCTEON_IS_MODEL(OCTEON_CN63XX))
|
|
{
|
|
cvmx_sriox_status_reg_t status_reg;
|
|
/* For now skip qlm2 */
|
|
if (qlm == 2)
|
|
{
|
|
cvmx_gmxx_inf_mode_t inf_mode;
|
|
inf_mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(0));
|
|
if (inf_mode.s.speed == 15)
|
|
return -1;
|
|
else if(inf_mode.s.mode == 0)
|
|
return 1;
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|
else
|
|
return 2;
|
|
}
|
|
status_reg.u64 = cvmx_read_csr(CVMX_SRIOX_STATUS_REG(qlm));
|
|
if (status_reg.s.srio)
|
|
return 4;
|
|
else
|
|
return 3;
|
|
}
|
|
else if (OCTEON_IS_MODEL(OCTEON_CN61XX))
|
|
{
|
|
qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
|
|
/* QLM is disabled when QLM SPD is 15. */
|
|
if (qlmx_cfg.s.qlm_spd == 15)
|
|
return -1;
|
|
|
|
switch(qlm)
|
|
{
|
|
case 0:
|
|
switch (qlmx_cfg.s.qlm_cfg)
|
|
{
|
|
case 0: /* PCIe 1x4 gen2 / gen1 */
|
|
return 3;
|
|
case 2: /* SGMII */
|
|
return 1;
|
|
case 3: /* XAUI */
|
|
return 2;
|
|
default: return -1;
|
|
}
|
|
break;
|
|
case 1:
|
|
switch (qlmx_cfg.s.qlm_cfg)
|
|
{
|
|
case 0: /* PCIe 1x2 gen2 / gen1 */
|
|
return 7;
|
|
case 1: /* PCIe 2x1 gen2 / gen1 */
|
|
return 8;
|
|
default: return -1;
|
|
}
|
|
break;
|
|
case 2:
|
|
switch (qlmx_cfg.s.qlm_cfg)
|
|
{
|
|
case 2: /* SGMII */
|
|
return 1;
|
|
case 3: /* XAUI */
|
|
return 2;
|
|
default: return -1;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
else if (OCTEON_IS_MODEL(OCTEON_CNF71XX))
|
|
{
|
|
qlmx_cfg.u64 = cvmx_read_csr(CVMX_MIO_QLMX_CFG(qlm));
|
|
/* QLM is disabled when QLM SPD is 15. */
|
|
if (qlmx_cfg.s.qlm_spd == 15)
|
|
return -1;
|
|
|
|
switch(qlm)
|
|
{
|
|
case 0:
|
|
if (qlmx_cfg.s.qlm_cfg == 2) /* SGMII */
|
|
return 1;
|
|
break;
|
|
case 1:
|
|
switch (qlmx_cfg.s.qlm_cfg)
|
|
{
|
|
case 0: /* PCIe 1x2 gen2 / gen1 */
|
|
return 7;
|
|
case 1: /* PCIe 2x1 gen2 / gen1 */
|
|
return 8;
|
|
default: return -1;
|
|
}
|
|
break;
|
|
}
|
|
}
|
|
return -1;
|
|
}
|