285 lines
9.9 KiB
C
285 lines
9.9 KiB
C
/*-
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* Copyright (C) 2007
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* Oleksandr Tymoshenko <gonzo@freebsd.org>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef __IF_KRREG_H__
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#define __IF_KRREG_H__
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#define KR_ETHINTFC 0x0000 /* Ethernet interface control */
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#define ETH_INTFC_EN 0x0001
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#define ETH_INTFC_RIP 0x0004
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#define ETH_INTFC_EN 0x0001
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#define KR_ETHFIFOTT 0x0004 /* Ethernet FIFO transmit threshold */
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#define KR_ETHARC 0x0008 /* Ethernet address recognition control */
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#define KR_ETHHASH0 0x000C /* Ethernet hash table 0 */
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#define KR_ETHHASH1 0x0010 /* Ethernet hash table 1 */
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#define KR_ETHPFS 0x0024 /* Ethernet pause frame status */
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#define KR_ETHMCP 0x0028 /* Ethernet management clock prescalar */
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#define KR_ETHSAL0 0x0100 /* Ethernet station address 0 low */
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#define KR_ETHSAH0 0x0104 /* Ethernet station address 0 high */
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#define KR_ETHSAL1 0x0108 /* Ethernet station address 1 low */
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#define KR_ETHSAH1 0x010C /* Ethernet station address 1 high */
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#define KR_ETHSAL2 0x0110 /* Ethernet station address 2 low */
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#define KR_ETHSAH2 0x0114 /* Ethernet station address 2 high */
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#define KR_ETHSAL3 0x0118 /* Ethernet station address 3 low */
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#define KR_ETHSAH3 0x011C /* Ethernet station address 3 high */
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#define KR_ETHRBC 0x0120 /* Ethernet receive byte count */
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#define KR_ETHRPC 0x0124 /* Ethernet receive packet count */
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#define KR_ETHRUPC 0x0128 /* Ethernet receive undersized packet cnt */
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#define KR_ETHRFC 0x012C /* Ethernet receive fragment count */
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#define KR_ETHTBC 0x0130 /* Ethernet transmit byte count */
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#define KR_ETHGPF 0x0134 /* Ethernet generate pause frame */
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#define KR_ETHMAC1 0x0200 /* Ethernet MAC configuration 1 */
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#define KR_ETH_MAC1_RE 0x01
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#define KR_ETH_MAC1_PAF 0x02
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#define KR_ETH_MAC1_MR 0x80
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#define KR_ETHMAC2 0x0204 /* Ethernet MAC configuration 2 */
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#define KR_ETH_MAC2_FD 0x01
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#define KR_ETH_MAC2_FLC 0x02
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#define KR_ETH_MAC2_HFE 0x04
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#define KR_ETH_MAC2_DC 0x08
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#define KR_ETH_MAC2_CEN 0x10
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#define KR_ETH_MAC2_PEN 0x20
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#define KR_ETH_MAC2_VPE 0x08
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#define KR_ETHIPGT 0x0208 /* Ethernet back-to-back inter-packet gap */
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#define KR_ETHIPGR 0x020C /* Ethernet non back-to-back inter-packet gap */
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#define KR_ETHCLRT 0x0210 /* Ethernet collision window retry */
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#define KR_ETHMAXF 0x0214 /* Ethernet maximum frame length */
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#define KR_ETHMTEST 0x021C /* Ethernet MAC test */
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#define KR_MIIMCFG 0x0220 /* MII management configuration */
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#define KR_MIIMCFG_R 0x8000
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#define KR_MIIMCMD 0x0224 /* MII management command */
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#define KR_MIIMCMD_RD 0x01
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#define KR_MIIMCMD_SCN 0x02
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#define KR_MIIMADDR 0x0228 /* MII management address */
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#define KR_MIIMWTD 0x022C /* MII management write data */
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#define KR_MIIMRDD 0x0230 /* MII management read data */
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#define KR_MIIMIND 0x0234 /* MII management indicators */
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#define KR_MIIMIND_BSY 0x1
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#define KR_MIIMIND_SCN 0x2
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#define KR_MIIMIND_NV 0x4
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#define KR_ETHCFSA0 0x0240 /* Ethernet control frame station address 0 */
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#define KR_ETHCFSA1 0x0244 /* Ethernet control frame station address 1 */
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#define KR_ETHCFSA2 0x0248 /* Ethernet control frame station address 2 */
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#define KR_ETHIPGT_HALF_DUPLEX 0x12
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#define KR_ETHIPGT_FULL_DUPLEX 0x15
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#define KR_TIMEOUT 0xf000
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#define KR_MII_TIMEOUT 0xf000
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#define KR_RX_IRQ 40
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#define KR_TX_IRQ 41
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#define KR_RX_UND_IRQ 42
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#define KR_TX_OVR_IRQ 43
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#define RC32434_DMA_BASE_ADDR MIPS_PHYS_TO_KSEG1(0x18040000)
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#define DMA_C 0x00
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#define DMA_C_R 0x01
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#define DMA_C_ABORT 0x10
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#define DMA_S 0x04
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#define DMA_S_F 0x01
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#define DMA_S_D 0x02
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#define DMA_S_C 0x04
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#define DMA_S_E 0x08
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#define DMA_S_H 0x10
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#define DMA_SM 0x08
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#define DMA_SM_F 0x01
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#define DMA_SM_D 0x02
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#define DMA_SM_C 0x04
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#define DMA_SM_E 0x08
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#define DMA_SM_H 0x10
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#define DMA_DPTR 0x0C
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#define DMA_NDPTR 0x10
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#define RC32434_DMA_CHAN_SIZE 0x14
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#define KR_DMA_RXCHAN 0
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#define KR_DMA_TXCHAN 1
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#define KR_DMA_READ_REG(chan, reg) \
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(*(volatile uint32_t *) \
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(RC32434_DMA_BASE_ADDR + chan * RC32434_DMA_CHAN_SIZE + reg))
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#define KR_DMA_WRITE_REG(chan, reg, val) \
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((*(volatile uint32_t *) \
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(RC32434_DMA_BASE_ADDR + chan * RC32434_DMA_CHAN_SIZE + reg)) = val)
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#define KR_DMA_SETBITS_REG(chan, reg, bits) \
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KR_DMA_WRITE_REG((chan), (reg), KR_DMA_READ_REG((chan), (reg)) | (bits))
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#define KR_DMA_CLEARBITS_REG(chan, reg, bits) \
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KR_DMA_WRITE_REG((chan), (reg), \
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KR_DMA_READ_REG((chan), (reg)) & ~(bits))
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struct kr_desc {
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uint32_t kr_ctl;
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uint32_t kr_ca;
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uint32_t kr_devcs;
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uint32_t kr_link;
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};
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#define KR_DMASIZE(len) ((len) & ((1 << 18)-1))
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#define KR_PKTSIZE(len) ((len & 0xffff0000) >> 16)
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#define KR_CTL_COF 0x02000000
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#define KR_CTL_COD 0x04000000
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#define KR_CTL_IOF 0x08000000
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#define KR_CTL_IOD 0x10000000
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#define KR_CTL_T 0x20000000
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#define KR_CTL_D 0x40000000
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#define KR_CTL_F 0x80000000
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#define KR_DMARX_DEVCS_RSV 0x00000001
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#define KR_DMARX_DEVCS_LD 0x00000002
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#define KR_DMARX_DEVCS_ROK 0x00000004
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#define KR_DMARX_DEVCS_FM 0x00000008
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#define KR_DMARX_DEVCS_MP 0x00000010
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#define KR_DMARX_DEVCS_BP 0x00000020
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#define KR_DMARX_DEVCS_VLT 0x00000040
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#define KR_DMARX_DEVCS_CF 0x00000080
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#define KR_DMARX_DEVCS_OVR 0x00000100
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#define KR_DMARX_DEVCS_CRC 0x00000200
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#define KR_DMARX_DEVCS_CV 0x00000400
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#define KR_DMARX_DEVCS_DB 0x00000800
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#define KR_DMARX_DEVCS_LE 0x00001000
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#define KR_DMARX_DEVCS_LOR 0x00002000
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#define KR_DMARX_DEVCS_CES 0x00004000
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#define KR_DMATX_DEVCS_FD 0x00000001
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#define KR_DMATX_DEVCS_LD 0x00000002
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#define KR_DMATX_DEVCS_OEN 0x00000004
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#define KR_DMATX_DEVCS_PEN 0x00000008
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#define KR_DMATX_DEVCS_CEN 0x00000010
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#define KR_DMATX_DEVCS_HEN 0x00000020
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#define KR_DMATX_DEVCS_TOK 0x00000040
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#define KR_DMATX_DEVCS_MP 0x00000080
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#define KR_DMATX_DEVCS_BP 0x00000100
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#define KR_DMATX_DEVCS_UND 0x00000200
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#define KR_DMATX_DEVCS_OF 0x00000400
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#define KR_DMATX_DEVCS_ED 0x00000800
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#define KR_DMATX_DEVCS_EC 0x00001000
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#define KR_DMATX_DEVCS_LC 0x00002000
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#define KR_DMATX_DEVCS_TD 0x00004000
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#define KR_DMATX_DEVCS_CRC 0x00008000
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#define KR_DMATX_DEVCS_LE 0x00010000
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#define KR_RX_RING_CNT 128
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#define KR_TX_RING_CNT 128
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#define KR_TX_RING_SIZE sizeof(struct kr_desc) * KR_TX_RING_CNT
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#define KR_RX_RING_SIZE sizeof(struct kr_desc) * KR_RX_RING_CNT
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#define KR_RING_ALIGN sizeof(struct kr_desc)
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#define KR_RX_ALIGN sizeof(uint32_t)
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#define KR_MAXFRAGS 8
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#define KR_TX_INTR_THRESH 8
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#define KR_TX_RING_ADDR(sc, i) \
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((sc)->kr_rdata.kr_tx_ring_paddr + sizeof(struct kr_desc) * (i))
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#define KR_RX_RING_ADDR(sc, i) \
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((sc)->kr_rdata.kr_rx_ring_paddr + sizeof(struct kr_desc) * (i))
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#define KR_INC(x,y) (x) = (((x) + 1) % y)
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struct kr_txdesc {
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struct mbuf *tx_m;
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bus_dmamap_t tx_dmamap;
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};
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struct kr_rxdesc {
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struct mbuf *rx_m;
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bus_dmamap_t rx_dmamap;
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struct kr_desc *desc;
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/* Use this values on error instead of allocating new mbuf */
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uint32_t saved_ctl, saved_ca;
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};
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struct kr_chain_data {
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bus_dma_tag_t kr_parent_tag;
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bus_dma_tag_t kr_tx_tag;
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struct kr_txdesc kr_txdesc[KR_TX_RING_CNT];
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bus_dma_tag_t kr_rx_tag;
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struct kr_rxdesc kr_rxdesc[KR_RX_RING_CNT];
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bus_dma_tag_t kr_tx_ring_tag;
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bus_dma_tag_t kr_rx_ring_tag;
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bus_dmamap_t kr_tx_ring_map;
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bus_dmamap_t kr_rx_ring_map;
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bus_dmamap_t kr_rx_sparemap;
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int kr_tx_pkts;
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int kr_tx_prod;
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int kr_tx_cons;
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int kr_tx_cnt;
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int kr_rx_cons;
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};
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struct kr_ring_data {
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struct kr_desc *kr_rx_ring;
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struct kr_desc *kr_tx_ring;
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bus_addr_t kr_rx_ring_paddr;
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bus_addr_t kr_tx_ring_paddr;
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};
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struct kr_softc {
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struct ifnet *kr_ifp; /* interface info */
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bus_space_handle_t kr_bhandle; /* bus space handle */
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bus_space_tag_t kr_btag; /* bus space tag */
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device_t kr_dev;
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struct resource *kr_res;
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int kr_rid;
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struct resource *kr_rx_irq;
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void *kr_rx_intrhand;
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struct resource *kr_tx_irq;
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void *kr_tx_intrhand;
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struct resource *kr_rx_und_irq;
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void *kr_rx_und_intrhand;
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struct resource *kr_tx_ovr_irq;
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void *kr_tx_ovr_intrhand;
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device_t kr_miibus;
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bus_dma_tag_t kr_parent_tag;
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bus_dma_tag_t kr_tag;
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struct mtx kr_mtx;
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struct callout kr_stat_callout;
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struct task kr_link_task;
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struct kr_chain_data kr_cdata;
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struct kr_ring_data kr_rdata;
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int kr_link_status;
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int kr_detach;
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};
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#define KR_LOCK(_sc) mtx_lock(&(_sc)->kr_mtx)
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#define KR_UNLOCK(_sc) mtx_unlock(&(_sc)->kr_mtx)
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#define KR_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->kr_mtx, MA_OWNED)
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/*
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* register space access macros
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*/
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#define CSR_WRITE_4(sc, reg, val) \
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bus_space_write_4(sc->kr_btag, sc->kr_bhandle, reg, val)
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#define CSR_READ_4(sc, reg) \
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bus_space_read_4(sc->kr_btag, sc->kr_bhandle, reg)
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#endif /* __IF_KRREG_H__ */
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