136 lines
3.4 KiB
C
136 lines
3.4 KiB
C
/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2010-2016 Intel Corporation
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <rte_log.h>
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#include <rte_port_ring.h>
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#include <rte_table_stub.h>
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#include <rte_pipeline.h>
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#include "main.h"
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void
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app_main_loop_worker_pipeline_stub(void) {
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struct rte_pipeline_params pipeline_params = {
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.name = "pipeline",
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.socket_id = rte_socket_id(),
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};
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struct rte_pipeline *p;
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uint32_t port_in_id[APP_MAX_PORTS];
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uint32_t port_out_id[APP_MAX_PORTS];
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uint32_t table_id[APP_MAX_PORTS];
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uint32_t i;
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RTE_LOG(INFO, USER1, "Core %u is doing work (pipeline with stub "
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"tables)\n", rte_lcore_id());
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/* Pipeline configuration */
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p = rte_pipeline_create(&pipeline_params);
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if (p == NULL)
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rte_panic("Unable to configure the pipeline\n");
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/* Input port configuration */
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for (i = 0; i < app.n_ports; i++) {
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struct rte_port_ring_reader_params port_ring_params = {
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.ring = app.rings_rx[i],
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};
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struct rte_pipeline_port_in_params port_params = {
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.ops = &rte_port_ring_reader_ops,
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.arg_create = (void *) &port_ring_params,
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.f_action = NULL,
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.arg_ah = NULL,
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.burst_size = app.burst_size_worker_read,
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};
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if (rte_pipeline_port_in_create(p, &port_params,
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&port_in_id[i]))
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rte_panic("Unable to configure input port for "
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"ring %d\n", i);
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}
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/* Output port configuration */
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for (i = 0; i < app.n_ports; i++) {
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struct rte_port_ring_writer_params port_ring_params = {
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.ring = app.rings_tx[i],
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.tx_burst_sz = app.burst_size_worker_write,
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};
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struct rte_pipeline_port_out_params port_params = {
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.ops = &rte_port_ring_writer_ops,
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.arg_create = (void *) &port_ring_params,
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.f_action = NULL,
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.arg_ah = NULL,
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};
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if (rte_pipeline_port_out_create(p, &port_params,
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&port_out_id[i]))
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rte_panic("Unable to configure output port for "
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"ring %d\n", i);
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}
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/* Table configuration */
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for (i = 0; i < app.n_ports; i++) {
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struct rte_pipeline_table_params table_params = {
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.ops = &rte_table_stub_ops,
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.arg_create = NULL,
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.f_action_hit = NULL,
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.f_action_miss = NULL,
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.arg_ah = NULL,
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.action_data_size = 0,
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};
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if (rte_pipeline_table_create(p, &table_params, &table_id[i]))
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rte_panic("Unable to configure table %u\n", i);
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}
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/* Interconnecting ports and tables */
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for (i = 0; i < app.n_ports; i++)
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if (rte_pipeline_port_in_connect_to_table(p, port_in_id[i],
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table_id[i]))
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rte_panic("Unable to connect input port %u to "
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"table %u\n", port_in_id[i], table_id[i]);
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/* Add entries to tables */
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for (i = 0; i < app.n_ports; i++) {
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struct rte_pipeline_table_entry entry = {
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.action = RTE_PIPELINE_ACTION_PORT,
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{.port_id = port_out_id[i ^ 1]},
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};
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struct rte_pipeline_table_entry *default_entry_ptr;
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if (rte_pipeline_table_default_entry_add(p, table_id[i], &entry,
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&default_entry_ptr))
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rte_panic("Unable to add default entry to table %u\n",
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table_id[i]);
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}
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/* Enable input ports */
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for (i = 0; i < app.n_ports; i++)
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if (rte_pipeline_port_in_enable(p, port_in_id[i]))
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rte_panic("Unable to enable input port %u\n",
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port_in_id[i]);
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/* Check pipeline consistency */
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if (rte_pipeline_check(p) < 0)
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rte_panic("Pipeline consistency check failed\n");
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/* Run-time */
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#if APP_FLUSH == 0
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for ( ; ; )
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rte_pipeline_run(p);
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#else
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for (i = 0; ; i++) {
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rte_pipeline_run(p);
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if ((i & APP_FLUSH) == 0)
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rte_pipeline_flush(p);
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}
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#endif
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}
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