357 lines
8.9 KiB
C
357 lines
8.9 KiB
C
/*-
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* Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ddb.h"
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#include <sys/param.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/cons.h>
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#include <sys/kdb.h>
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#include <sys/reboot.h>
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#include <vm/vm.h>
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#include <vm/vm_page.h>
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#include <net/ethernet.h>
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#include <machine/clock.h>
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#include <machine/cpu.h>
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#include <machine/cpuregs.h>
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#include <machine/hwfunc.h>
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#include <machine/md_var.h>
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#include <machine/trap.h>
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#include <machine/vmparam.h>
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#include <mips/atheros/ar71xxreg.h>
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#include <mips/atheros/ar933xreg.h>
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#include <mips/atheros/ar71xx_cpudef.h>
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#include <mips/atheros/ar71xx_setup.h>
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#include <mips/atheros/ar71xx_chip.h>
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#include <mips/atheros/ar933x_chip.h>
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static void
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ar933x_chip_detect_mem_size(void)
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{
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}
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static void
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ar933x_chip_detect_sys_frequency(void)
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{
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uint32_t clock_ctrl;
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uint32_t cpu_config;
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uint32_t freq;
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uint32_t t;
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t = ATH_READ_REG(AR933X_RESET_REG_BOOTSTRAP);
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if (t & AR933X_BOOTSTRAP_REF_CLK_40)
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u_ar71xx_refclk = (40 * 1000 * 1000);
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else
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u_ar71xx_refclk = (25 * 1000 * 1000);
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clock_ctrl = ATH_READ_REG(AR933X_PLL_CLOCK_CTRL_REG);
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if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
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u_ar71xx_cpu_freq = u_ar71xx_refclk;
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u_ar71xx_ahb_freq = u_ar71xx_refclk;
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u_ar71xx_ddr_freq = u_ar71xx_refclk;
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} else {
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cpu_config = ATH_READ_REG(AR933X_PLL_CPU_CONFIG_REG);
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t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
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freq = u_ar71xx_refclk / t;
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t = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
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AR933X_PLL_CPU_CONFIG_NINT_MASK;
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freq *= t;
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t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
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if (t == 0)
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t = 1;
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freq >>= t;
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t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
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AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
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u_ar71xx_cpu_freq = freq / t;
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t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
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AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
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u_ar71xx_ddr_freq = freq / t;
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t = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
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AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
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u_ar71xx_ahb_freq = freq / t;
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}
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/*
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* On the AR933x, the UART frequency is the reference clock,
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* not the AHB bus clock.
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*/
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u_ar71xx_uart_freq = u_ar71xx_refclk;
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/*
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* XXX TODO: check whether the mdio frequency is always the
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* refclock frequency, or whether it's variable like on the
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* AR934x.
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*/
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u_ar71xx_mdio_freq = u_ar71xx_refclk;
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/*
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* XXX check what the watchdog frequency should be?
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*/
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u_ar71xx_wdt_freq = u_ar71xx_ahb_freq;
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}
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static void
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ar933x_chip_device_stop(uint32_t mask)
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{
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uint32_t reg;
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reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
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ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg | mask);
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}
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static void
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ar933x_chip_device_start(uint32_t mask)
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{
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uint32_t reg;
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reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
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ATH_WRITE_REG(AR933X_RESET_REG_RESET_MODULE, reg & ~mask);
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}
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static int
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ar933x_chip_device_stopped(uint32_t mask)
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{
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uint32_t reg;
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reg = ATH_READ_REG(AR933X_RESET_REG_RESET_MODULE);
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return ((reg & mask) == mask);
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}
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static void
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ar933x_chip_set_mii_speed(uint32_t unit, uint32_t speed)
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{
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/* XXX TODO */
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return;
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}
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/*
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* XXX TODO !!
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*/
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static void
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ar933x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
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{
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switch (unit) {
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case 0:
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/* XXX TODO */
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break;
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case 1:
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/* XXX TODO */
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break;
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default:
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printf("%s: invalid PLL set for arge unit: %d\n",
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__func__, unit);
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return;
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}
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}
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static void
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ar933x_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
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{
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switch (id) {
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case AR71XX_CPU_DDR_FLUSH_GE0:
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ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0);
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break;
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case AR71XX_CPU_DDR_FLUSH_GE1:
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ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1);
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break;
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case AR71XX_CPU_DDR_FLUSH_USB:
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ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_USB);
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break;
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case AR71XX_CPU_DDR_FLUSH_WMAC:
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ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_WMAC);
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break;
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default:
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printf("%s: invalid DDR flush id (%d)\n", __func__, id);
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break;
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}
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}
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static uint32_t
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ar933x_chip_get_eth_pll(unsigned int mac, int speed)
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{
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uint32_t pll;
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switch (speed) {
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case 10:
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pll = AR933X_PLL_VAL_10;
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break;
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case 100:
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pll = AR933X_PLL_VAL_100;
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break;
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case 1000:
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pll = AR933X_PLL_VAL_1000;
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break;
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default:
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printf("%s%d: invalid speed %d\n", __func__, mac, speed);
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pll = 0;
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}
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return (pll);
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}
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static void
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ar933x_chip_init_usb_peripheral(void)
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{
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ar71xx_device_stop(AR933X_RESET_USBSUS_OVERRIDE);
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DELAY(100);
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ar71xx_device_start(AR933X_RESET_USB_HOST);
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DELAY(100);
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ar71xx_device_start(AR933X_RESET_USB_PHY);
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DELAY(100);
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}
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static void
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ar933x_configure_gmac(uint32_t gmac_cfg)
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{
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uint32_t reg;
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reg = ATH_READ_REG(AR933X_GMAC_REG_ETH_CFG);
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/*
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* The relevant bits here include:
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*
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* + AR933X_ETH_CFG_SW_PHY_SWAP
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* + AR933X_ETH_CFG_SW_PHY_ADDR_SWAP
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*
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* There are other things; look at what openwrt exposes so
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* it can be correctly exposed.
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*
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* TODO: what about ethernet switch support? How's that work?
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*/
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if (bootverbose)
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printf("%s: GMAC config was 0x%08x\n", __func__, reg);
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reg &= ~(AR933X_ETH_CFG_SW_PHY_SWAP | AR933X_ETH_CFG_SW_PHY_ADDR_SWAP);
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reg |= gmac_cfg;
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if (bootverbose)
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printf("%s: GMAC setting is 0x%08x; register is now 0x%08x\n",
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__func__,
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gmac_cfg,
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reg);
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ATH_WRITE_REG(AR933X_GMAC_REG_ETH_CFG, reg);
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}
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static void
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ar933x_chip_init_gmac(void)
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{
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int val;
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uint32_t gmac_cfg = 0;
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/*
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* These two bits need a bit better explanation.
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*
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* The default configuration in the hardware is to map both
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* ports to the internal switch.
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*
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* Here, GE0 == arge0, GE1 == arge1.
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*
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* The internal switch has:
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* + 5 MAC ports, MAC0->MAC4.
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* + 5 PHY ports, PHY0->PHY4,
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* + MAC0 connects to GE1;
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* + GE0 connects to PHY4;
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* + The other mappings are MAC1->PHY0, MAC2->PHY1 .. MAC4->PHY3.
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*
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* The GE1 port is linked in via 1000MBit/full, supplying what is
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* normally the 'WAN' switch ports.
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*
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* The switch is connected the MDIO bus on GE1. It looks like
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* a normal AR7240 on-board switch.
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*
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* The GE0 port is connected via MII to PHY4, and can operate in
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* 10/100mbit, full/half duplex. Ie, you can speak to PHY4 on
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* the MDIO bus and everything will simply 'work'.
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*
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* So far so good. This looks just like an AR7240 SoC.
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*
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* However, some configurations will just expose one or two
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* physical ports. In this case, some configuration bits can
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* be set to tweak this.
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*
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* + CFG_SW_PHY_ADDR_SWAP swaps PHY port 0 with PHY port 4.
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* Ie, GE0's PHY shows up as PHY 0. So if there's only
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* one physical port, there's no need to involve the
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* switch framework - it can just show up as a default,
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* normal single PHY.
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*
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* + CFG_SW_PHY_SWAP swaps the internal switch connection
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* between PHY0 and PHY4. Ie, PHY4 connects to MAc1,
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* PHY0 connects to GE0.
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*/
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if ((resource_int_value("ar933x_gmac", 0, "override_phy", &val) == 0)
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&& (val == 0))
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return;
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if ((resource_int_value("ar933x_gmac", 0, "swap_phy", &val) == 0)
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&& (val == 1))
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gmac_cfg |= AR933X_ETH_CFG_SW_PHY_SWAP;
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if ((resource_int_value("ar933x_gmac", 0, "swap_phy_addr", &val) == 0)
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&& (val == 1))
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gmac_cfg |= AR933X_ETH_CFG_SW_PHY_ADDR_SWAP;
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ar933x_configure_gmac(gmac_cfg);
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}
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struct ar71xx_cpu_def ar933x_chip_def = {
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&ar933x_chip_detect_mem_size,
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&ar933x_chip_detect_sys_frequency,
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&ar933x_chip_device_stop,
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&ar933x_chip_device_start,
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&ar933x_chip_device_stopped,
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&ar933x_chip_set_pll_ge,
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&ar933x_chip_set_mii_speed,
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&ar71xx_chip_set_mii_if,
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&ar933x_chip_get_eth_pll,
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&ar933x_chip_ddr_flush,
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&ar933x_chip_init_usb_peripheral,
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NULL,
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NULL,
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&ar933x_chip_init_gmac,
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};
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