150 lines
5.6 KiB
C
150 lines
5.6 KiB
C
/*-
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* Copyright (c) 2010 Juli Mallett <jmallett@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Register definitions for Marvell MV88E61XX
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*
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* Note that names and definitions were gleaned from Linux and U-Boot patches
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* released by Marvell, often by looking at contextual use of the registers
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* involved, and may not be representative of the full functionality of those
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* registers and are certainly not an exhaustive enumeration of registers.
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*
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* For an exhaustive enumeration of registers, check out the QD-DSDT package
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* included in the Marvell ARM Feroceon Board Support Package for Linux.
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*/
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#ifndef _MIPS_CAVIUM_OCTE_MV88E61XXPHYREG_H_
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#define _MIPS_CAVIUM_OCTE_MV88E61XXPHYREG_H_
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/*
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* Port addresses & per-port registers.
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*/
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#define MV88E61XX_PORT(x) (0x10 + (x))
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#define MV88E61XX_HOST_PORT (5)
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#define MV88E61XX_PORTS (6)
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#define MV88E61XX_PORT_STATUS (0x00)
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#define MV88E61XX_PORT_FORCE_MAC (0x01)
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#define MV88E61XX_PORT_PAUSE_CONTROL (0x02)
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#define MV88E61XX_PORT_REVISION (0x03)
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#define MV88E61XX_PORT_CONTROL (0x04)
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#define MV88E61XX_PORT_CONTROL2 (0x05)
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#define MV88E61XX_PORT_VLAN_MAP (0x06)
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#define MV88E61XX_PORT_VLAN (0x07)
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#define MV88E61XX_PORT_FILTER (0x08)
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#define MV88E61XX_PORT_EGRESS_CONTROL (0x09)
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#define MV88E61XX_PORT_EGRESS_CONTROL2 (0x0a)
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#define MV88E61XX_PORT_PORT_LEARN (0x0b)
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#define MV88E61XX_PORT_ATU_CONTROL (0x0c)
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#define MV88E61XX_PORT_PRIORITY_CONTROL (0x0d)
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#define MV88E61XX_PORT_ETHER_PROTO (0x0f)
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#define MV88E61XX_PORT_PROVIDER_PROTO (0x1a)
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#define MV88E61XX_PORT_PRIORITY_MAP (0x18)
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#define MV88E61XX_PORT_PRIORITY_MAP2 (0x19)
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/*
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* Fields and values in each register.
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*/
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#define MV88E61XX_PORT_STATUS_MEDIA (0x0300)
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#define MV88E61XX_PORT_STATUS_MEDIA_10M (0x0000)
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#define MV88E61XX_PORT_STATUS_MEDIA_100M (0x0100)
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#define MV88E61XX_PORT_STATUS_MEDIA_1G (0x0200)
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#define MV88E61XX_PORT_STATUS_DUPLEX (0x0400)
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#define MV88E61XX_PORT_STATUS_LINK (0x0800)
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#define MV88E61XX_PORT_STATUS_FC (0x8000)
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#define MV88E61XX_PORT_CONTROL_DOUBLE_TAG (0x0200)
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#define MV88E61XX_PORT_FILTER_MAP_DEST (0x0080)
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#define MV88E61XX_PORT_FILTER_DISCARD_UNTAGGED (0x0100)
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#define MV88E61XX_PORT_FILTER_DISCARD_TAGGED (0x0200)
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#define MV88E61XX_PORT_FILTER_8021Q_MODE (0x0c00)
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#define MV88E61XX_PORT_FILTER_8021Q_DISABLED (0x0000)
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#define MV88E61XX_PORT_FILTER_8021Q_FALLBACK (0x0400)
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#define MV88E61XX_PORT_FILTER_8021Q_CHECK (0x0800)
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#define MV88E61XX_PORT_FILTER_8021Q_SECURE (0x0c00)
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/*
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* Global address & global registers.
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*/
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#define MV88E61XX_GLOBAL (0x1b)
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#define MV88E61XX_GLOBAL_STATUS (0x00)
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#define MV88E61XX_GLOBAL_CONTROL (0x04)
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#define MV88E61XX_GLOBAL_VTU_OP (0x05)
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#define MV88E61XX_GLOBAL_VTU_VID (0x06)
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#define MV88E61XX_GLOBAL_VTU_DATA_P0P3 (0x07)
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#define MV88E61XX_GLOBAL_VTU_DATA_P4P5 (0x08)
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#define MV88E61XX_GLOBAL_ATU_CONTROL (0x0a)
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#define MV88E61XX_GLOBAL_PRIORITY_MAP (0x18)
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#define MV88E61XX_GLOBAL_MONITOR (0x1a)
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#define MV88E61XX_GLOBAL_REMOTE_MGMT (0x1c)
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#define MV88E61XX_GLOBAL_STATS (0x1d)
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/*
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* Fields and values in each register.
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*/
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#define MV88E61XX_GLOBAL_VTU_OP_BUSY (0x8000)
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#define MV88E61XX_GLOBAL_VTU_OP_OP (0x7000)
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#define MV88E61XX_GLOBAL_VTU_OP_OP_FLUSH (0x1000)
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#define MV88E61XX_GLOBAL_VTU_OP_OP_VTU_LOAD (0x3000)
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#define MV88E61XX_GLOBAL_VTU_VID_VALID (0x1000)
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/*
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* Second global address & second global registers.
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*/
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#define MV88E61XX_GLOBAL2 (0x1c)
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#define MV88E61XX_GLOBAL2_MANAGE_2X (0x02)
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#define MV88E61XX_GLOBAL2_MANAGE_0X (0x03)
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#define MV88E61XX_GLOBAL2_CONTROL2 (0x05)
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#define MV88E61XX_GLOBAL2_TRUNK_MASK (0x07)
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#define MV88E61XX_GLOBAL2_TRUNK_MAP (0x08)
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#define MV88E61XX_GLOBAL2_RATELIMIT (0x09)
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#define MV88E61XX_GLOBAL2_VLAN_CONTROL (0x0b)
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#define MV88E61XX_GLOBAL2_MAC_ADDRESS (0x0d)
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/*
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* Fields and values in each register.
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*/
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#define MV88E61XX_GLOBAL2_CONTROL2_DOUBLE_USE (0x8000)
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#define MV88E61XX_GLOBAL2_CONTROL2_LOOP_PREVENT (0x4000)
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#define MV88E61XX_GLOBAL2_CONTROL2_FLOW_MESSAGE (0x2000)
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#define MV88E61XX_GLOBAL2_CONTROL2_FLOOD_BC (0x1000)
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#define MV88E61XX_GLOBAL2_CONTROL2_REMOVE_PTAG (0x0800)
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#define MV88E61XX_GLOBAL2_CONTROL2_AGE_INT (0x0400)
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#define MV88E61XX_GLOBAL2_CONTROL2_FLOW_TAG (0x0200)
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#define MV88E61XX_GLOBAL2_CONTROL2_ALWAYS_VTU (0x0100)
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#define MV88E61XX_GLOBAL2_CONTROL2_FORCE_FC_PRI (0x0080)
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#define MV88E61XX_GLOBAL2_CONTROL2_FC_PRI (0x0070)
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#define MV88E61XX_GLOBAL2_CONTROL2_MGMT_TO_HOST (0x0008)
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#define MV88E61XX_GLOBAL2_CONTROL2_MGMT_PRI (0x0007)
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#endif /* !_MIPS_CAVIUM_OCTE_MV88E61XXPHYREG_H_ */
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