507 lines
12 KiB
C
507 lines
12 KiB
C
/*-
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* Copyright (c) 2011, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* GPIO driver for Cavium Octeon
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/gpio.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <contrib/octeon-sdk/cvmx.h>
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#include <contrib/octeon-sdk/cvmx-gpio.h>
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#include <mips/cavium/octeon_irq.h>
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#include <mips/cavium/octeon_gpiovar.h>
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#include <dev/gpio/gpiobusvar.h>
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#include "gpio_if.h"
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#define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
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struct octeon_gpio_pin {
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const char *name;
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int pin;
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int flags;
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};
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/*
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* on CAP100 GPIO 7 is "Factory defaults" button
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*
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*/
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static struct octeon_gpio_pin octeon_gpio_pins[] = {
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{ "F/D", 7, GPIO_PIN_INPUT},
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{ NULL, 0, 0},
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};
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/*
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* Helpers
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*/
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static void octeon_gpio_pin_configure(struct octeon_gpio_softc *sc,
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struct gpio_pin *pin, uint32_t flags);
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/*
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* Driver stuff
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*/
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static void octeon_gpio_identify(driver_t *, device_t);
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static int octeon_gpio_probe(device_t dev);
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static int octeon_gpio_attach(device_t dev);
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static int octeon_gpio_detach(device_t dev);
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static int octeon_gpio_filter(void *arg);
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static void octeon_gpio_intr(void *arg);
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/*
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* GPIO interface
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*/
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static device_t octeon_gpio_get_bus(device_t);
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static int octeon_gpio_pin_max(device_t dev, int *maxpin);
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static int octeon_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps);
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static int octeon_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t
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*flags);
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static int octeon_gpio_pin_getname(device_t dev, uint32_t pin, char *name);
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static int octeon_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags);
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static int octeon_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value);
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static int octeon_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val);
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static int octeon_gpio_pin_toggle(device_t dev, uint32_t pin);
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static void
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octeon_gpio_pin_configure(struct octeon_gpio_softc *sc, struct gpio_pin *pin,
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unsigned int flags)
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{
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uint32_t mask;
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cvmx_gpio_bit_cfgx_t gpio_cfgx;
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mask = 1 << pin->gp_pin;
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GPIO_LOCK(sc);
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/*
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* Manage input/output
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*/
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if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) {
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gpio_cfgx.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(pin->gp_pin));
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pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT);
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if (flags & GPIO_PIN_OUTPUT) {
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pin->gp_flags |= GPIO_PIN_OUTPUT;
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gpio_cfgx.s.tx_oe = 1;
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}
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else {
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pin->gp_flags |= GPIO_PIN_INPUT;
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gpio_cfgx.s.tx_oe = 0;
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}
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if (flags & GPIO_PIN_INVIN)
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gpio_cfgx.s.rx_xor = 1;
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else
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gpio_cfgx.s.rx_xor = 0;
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cvmx_write_csr(CVMX_GPIO_BIT_CFGX(pin->gp_pin), gpio_cfgx.u64);
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}
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GPIO_UNLOCK(sc);
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}
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static device_t
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octeon_gpio_get_bus(device_t dev)
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{
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struct octeon_gpio_softc *sc;
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sc = device_get_softc(dev);
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return (sc->busdev);
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}
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static int
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octeon_gpio_pin_max(device_t dev, int *maxpin)
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{
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*maxpin = OCTEON_GPIO_PINS - 1;
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return (0);
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}
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static int
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octeon_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
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{
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struct octeon_gpio_softc *sc = device_get_softc(dev);
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int i;
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for (i = 0; i < sc->gpio_npins; i++) {
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if (sc->gpio_pins[i].gp_pin == pin)
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break;
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}
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if (i >= sc->gpio_npins)
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return (EINVAL);
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GPIO_LOCK(sc);
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*caps = sc->gpio_pins[i].gp_caps;
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GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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octeon_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
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{
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struct octeon_gpio_softc *sc = device_get_softc(dev);
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int i;
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for (i = 0; i < sc->gpio_npins; i++) {
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if (sc->gpio_pins[i].gp_pin == pin)
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break;
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}
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if (i >= sc->gpio_npins)
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return (EINVAL);
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GPIO_LOCK(sc);
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*flags = sc->gpio_pins[i].gp_flags;
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GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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octeon_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
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{
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struct octeon_gpio_softc *sc = device_get_softc(dev);
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int i;
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for (i = 0; i < sc->gpio_npins; i++) {
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if (sc->gpio_pins[i].gp_pin == pin)
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break;
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}
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if (i >= sc->gpio_npins)
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return (EINVAL);
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GPIO_LOCK(sc);
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memcpy(name, sc->gpio_pins[i].gp_name, GPIOMAXNAME);
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GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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octeon_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
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{
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int i;
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struct octeon_gpio_softc *sc = device_get_softc(dev);
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for (i = 0; i < sc->gpio_npins; i++) {
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if (sc->gpio_pins[i].gp_pin == pin)
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break;
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}
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if (i >= sc->gpio_npins)
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return (EINVAL);
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octeon_gpio_pin_configure(sc, &sc->gpio_pins[i], flags);
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return (0);
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}
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static int
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octeon_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
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{
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struct octeon_gpio_softc *sc = device_get_softc(dev);
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int i;
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for (i = 0; i < sc->gpio_npins; i++) {
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if (sc->gpio_pins[i].gp_pin == pin)
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break;
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}
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if (i >= sc->gpio_npins)
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return (EINVAL);
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GPIO_LOCK(sc);
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if (value)
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cvmx_gpio_set(1 << pin);
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else
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cvmx_gpio_clear(1 << pin);
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GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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octeon_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
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{
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struct octeon_gpio_softc *sc = device_get_softc(dev);
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int i;
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uint64_t state;
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for (i = 0; i < sc->gpio_npins; i++) {
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if (sc->gpio_pins[i].gp_pin == pin)
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break;
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}
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if (i >= sc->gpio_npins)
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return (EINVAL);
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GPIO_LOCK(sc);
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state = cvmx_gpio_read();
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*val = (state & (1 << pin)) ? 1 : 0;
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GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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octeon_gpio_pin_toggle(device_t dev, uint32_t pin)
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{
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int i;
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uint64_t state;
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struct octeon_gpio_softc *sc = device_get_softc(dev);
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for (i = 0; i < sc->gpio_npins; i++) {
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if (sc->gpio_pins[i].gp_pin == pin)
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break;
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}
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if (i >= sc->gpio_npins)
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return (EINVAL);
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GPIO_LOCK(sc);
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/*
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* XXX: Need to check if read returns actual state of output
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* pins or we need to keep this information by ourself
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*/
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state = cvmx_gpio_read();
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if (state & (1 << pin))
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cvmx_gpio_clear(1 << pin);
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else
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cvmx_gpio_set(1 << pin);
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GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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octeon_gpio_filter(void *arg)
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{
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cvmx_gpio_bit_cfgx_t gpio_cfgx;
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void **cookie = arg;
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struct octeon_gpio_softc *sc = *cookie;
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long int irq = (cookie - sc->gpio_intr_cookies);
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if ((irq < 0) || (irq >= OCTEON_GPIO_IRQS))
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return (FILTER_STRAY);
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gpio_cfgx.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(irq));
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/* Clear rising edge detector */
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if (gpio_cfgx.s.int_type == OCTEON_GPIO_IRQ_EDGE)
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cvmx_gpio_interrupt_clear(1 << irq);
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/* disable interrupt */
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gpio_cfgx.s.int_en = 0;
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cvmx_write_csr(CVMX_GPIO_BIT_CFGX(irq), gpio_cfgx.u64);
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return (FILTER_SCHEDULE_THREAD);
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}
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static void
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octeon_gpio_intr(void *arg)
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{
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cvmx_gpio_bit_cfgx_t gpio_cfgx;
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void **cookie = arg;
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struct octeon_gpio_softc *sc = *cookie;
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long int irq = (cookie - sc->gpio_intr_cookies);
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if ((irq < 0) || (irq >= OCTEON_GPIO_IRQS)) {
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printf("%s: invalid GPIO IRQ: %ld\n",
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__func__, irq);
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return;
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}
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GPIO_LOCK(sc);
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gpio_cfgx.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(irq));
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/* disable interrupt */
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gpio_cfgx.s.int_en = 1;
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cvmx_write_csr(CVMX_GPIO_BIT_CFGX(irq), gpio_cfgx.u64);
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/* TODO: notify bus here or something */
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printf("GPIO IRQ for pin %ld\n", irq);
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GPIO_UNLOCK(sc);
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}
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static void
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octeon_gpio_identify(driver_t *drv, device_t parent)
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{
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BUS_ADD_CHILD(parent, 0, "gpio", 0);
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}
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static int
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octeon_gpio_probe(device_t dev)
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{
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device_set_desc(dev, "Cavium Octeon GPIO driver");
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return (0);
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}
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static int
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octeon_gpio_attach(device_t dev)
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{
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struct octeon_gpio_softc *sc = device_get_softc(dev);
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struct octeon_gpio_pin *pinp;
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cvmx_gpio_bit_cfgx_t gpio_cfgx;
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int i;
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KASSERT((device_get_unit(dev) == 0),
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("octeon_gpio: Only one gpio module supported"));
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mtx_init(&sc->gpio_mtx, device_get_nameunit(dev), NULL, MTX_DEF);
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for ( i = 0; i < OCTEON_GPIO_IRQS; i++) {
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if ((sc->gpio_irq_res[i] = bus_alloc_resource(dev,
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SYS_RES_IRQ, &sc->gpio_irq_rid[i],
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OCTEON_IRQ_GPIO0 + i, OCTEON_IRQ_GPIO0 + i, 1,
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RF_SHAREABLE | RF_ACTIVE)) == NULL) {
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device_printf(dev, "unable to allocate IRQ resource\n");
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octeon_gpio_detach(dev);
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return (ENXIO);
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}
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sc->gpio_intr_cookies[i] = sc;
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if ((bus_setup_intr(dev, sc->gpio_irq_res[i], INTR_TYPE_MISC,
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octeon_gpio_filter, octeon_gpio_intr,
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&(sc->gpio_intr_cookies[i]), &sc->gpio_ih[i]))) {
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device_printf(dev,
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"WARNING: unable to register interrupt handler\n");
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octeon_gpio_detach(dev);
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return (ENXIO);
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}
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}
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sc->dev = dev;
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/* Configure all pins as input */
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/* disable interrupts for all pins */
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pinp = octeon_gpio_pins;
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i = 0;
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while (pinp->name) {
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strncpy(sc->gpio_pins[i].gp_name, pinp->name, GPIOMAXNAME);
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sc->gpio_pins[i].gp_pin = pinp->pin;
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sc->gpio_pins[i].gp_caps = DEFAULT_CAPS;
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sc->gpio_pins[i].gp_flags = 0;
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octeon_gpio_pin_configure(sc, &sc->gpio_pins[i], pinp->flags);
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pinp++;
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i++;
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}
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sc->gpio_npins = i;
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#if 0
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/*
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* Sample: how to enable edge-triggered interrupt
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* for GPIO pin
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*/
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gpio_cfgx.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(7));
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gpio_cfgx.s.int_en = 1;
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gpio_cfgx.s.int_type = OCTEON_GPIO_IRQ_EDGE;
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cvmx_write_csr(CVMX_GPIO_BIT_CFGX(7), gpio_cfgx.u64);
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#endif
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if (bootverbose) {
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for (i = 0; i < 16; i++) {
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gpio_cfgx.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(i));
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device_printf(dev, "[pin%d] output=%d, invinput=%d, intr=%d, intr_type=%s\n",
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i, gpio_cfgx.s.tx_oe, gpio_cfgx.s.rx_xor,
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gpio_cfgx.s.int_en, gpio_cfgx.s.int_type ? "rising edge" : "level");
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}
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}
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sc->busdev = gpiobus_attach_bus(dev);
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if (sc->busdev == NULL) {
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octeon_gpio_detach(dev);
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return (ENXIO);
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}
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return (0);
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}
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static int
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octeon_gpio_detach(device_t dev)
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{
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struct octeon_gpio_softc *sc = device_get_softc(dev);
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int i;
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KASSERT(mtx_initialized(&sc->gpio_mtx), ("gpio mutex not initialized"));
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for ( i = 0; i < OCTEON_GPIO_IRQS; i++) {
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if (sc->gpio_ih[i])
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bus_teardown_intr(dev, sc->gpio_irq_res[i],
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sc->gpio_ih[i]);
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if (sc->gpio_irq_res[i])
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bus_release_resource(dev, SYS_RES_IRQ,
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sc->gpio_irq_rid[i], sc->gpio_irq_res[i]);
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}
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gpiobus_detach_bus(dev);
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mtx_destroy(&sc->gpio_mtx);
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return(0);
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}
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static device_method_t octeon_gpio_methods[] = {
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DEVMETHOD(device_identify, octeon_gpio_identify),
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DEVMETHOD(device_probe, octeon_gpio_probe),
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DEVMETHOD(device_attach, octeon_gpio_attach),
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DEVMETHOD(device_detach, octeon_gpio_detach),
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/* GPIO protocol */
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DEVMETHOD(gpio_get_bus, octeon_gpio_get_bus),
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DEVMETHOD(gpio_pin_max, octeon_gpio_pin_max),
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DEVMETHOD(gpio_pin_getname, octeon_gpio_pin_getname),
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DEVMETHOD(gpio_pin_getflags, octeon_gpio_pin_getflags),
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DEVMETHOD(gpio_pin_getcaps, octeon_gpio_pin_getcaps),
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DEVMETHOD(gpio_pin_setflags, octeon_gpio_pin_setflags),
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DEVMETHOD(gpio_pin_get, octeon_gpio_pin_get),
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DEVMETHOD(gpio_pin_set, octeon_gpio_pin_set),
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DEVMETHOD(gpio_pin_toggle, octeon_gpio_pin_toggle),
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{0, 0},
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};
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static driver_t octeon_gpio_driver = {
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"gpio",
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octeon_gpio_methods,
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sizeof(struct octeon_gpio_softc),
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};
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static devclass_t octeon_gpio_devclass;
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DRIVER_MODULE(octeon_gpio, ciu, octeon_gpio_driver, octeon_gpio_devclass, 0, 0);
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