106 lines
3.6 KiB
C
106 lines
3.6 KiB
C
/***********************license start************************************
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* Copyright (c) 2005-2007 Cavium Networks (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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*
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* * Neither the name of Cavium Networks nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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*
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
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* OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
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* RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
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* REPRESENTATION OR DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT
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* DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
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* OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
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* PURPOSE, LACK OF VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET
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* POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
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* OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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*
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*
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* For any questions regarding licensing please contact marketing@caviumnetworks.com
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*
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***********************license end**************************************/
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/* $FreeBSD$ */
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#ifndef _CAVIUM_OCTOPCIREG_H_
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#define _CAVIUM_OCTOPCIREG_H_
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/**
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* This is the bit decoding used for the Octeon PCI controller addresses for config space
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*/
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typedef union
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{
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uint64_t u64;
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uint64_t * u64_ptr;
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uint32_t * u32_ptr;
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uint16_t * u16_ptr;
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uint8_t * u8_ptr;
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struct
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{
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uint64_t upper : 2;
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uint64_t reserved : 13;
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uint64_t io : 1;
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uint64_t did : 5;
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uint64_t subdid : 3;
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uint64_t reserved2 : 4;
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uint64_t endian_swap : 2;
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uint64_t reserved3 : 10;
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uint64_t bus : 8;
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uint64_t dev : 5;
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uint64_t func : 3;
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uint64_t reg : 8;
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} s;
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} octeon_pci_config_space_address_t;
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typedef union
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{
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uint64_t u64;
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uint32_t * u32_ptr;
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uint16_t * u16_ptr;
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uint8_t * u8_ptr;
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struct
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{
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uint64_t upper : 2;
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uint64_t reserved : 13;
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uint64_t io : 1;
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uint64_t did : 5;
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uint64_t subdid : 3;
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uint64_t reserved2 : 4;
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uint64_t endian_swap : 2;
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uint64_t res1 : 1;
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uint64_t port : 1;
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uint64_t addr : 32;
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} s;
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} octeon_pci_io_space_address_t;
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#define CVMX_OCT_SUBDID_PCI_CFG 1
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#define CVMX_OCT_SUBDID_PCI_IO 2
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#define CVMX_OCT_SUBDID_PCI_MEM1 3
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#define CVMX_OCT_SUBDID_PCI_MEM2 4
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#define CVMX_OCT_SUBDID_PCI_MEM3 5
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#define CVMX_OCT_SUBDID_PCI_MEM4 6
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#define CVMX_OCT_PCI_IO_BASE 0x00004000
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#define CVMX_OCT_PCI_IO_SIZE 0x08000000
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#define CVMX_OCT_PCI_MEM1_BASE 0xf0000000
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#define CVMX_OCT_PCI_MEM1_SIZE 0x0f000000
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#endif /* !_CAVIUM_OCTOPCIREG_H_ */
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