371 lines
8.6 KiB
C
371 lines
8.6 KiB
C
/*-
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* Copyright (c) 2016 Stanislav Galabov
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* Copyright (c) 2015 Alexander Kabaev
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include "opt_platform.h"
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/ktr.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
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#include <sys/cpuset.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/smp.h>
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#include <sys/sched.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/smp.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "pic_if.h"
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#define MTK_NIRQS 64 /* We'll only use 64 for now */
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#define MTK_INTPOL 0x0100
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#define MTK_INTTRIG 0x0180
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#define MTK_INTDIS 0x0300
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#define MTK_INTENA 0x0380
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#define MTK_INTMASK 0x0400
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#define MTK_INTSTAT 0x0480
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#define MTK_MAPPIN(_i) (0x0500 + (4 * (_i)))
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#define MTK_MAPVPE(_i, _v) (0x2000 + (32 * (_i)) + (((_v) / 32) * 4))
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#define MTK_INTPOL_POS 1
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#define MTK_INTPOL_NEG 0
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#define MTK_INTTRIG_EDGE 1
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#define MTK_INTTRIG_LEVEL 0
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#define MTK_PIN_BITS(_i) ((1 << 31) | (_i))
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#define MTK_VPE_BITS(_v) (1 << ((_v) % 32))
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static int mtk_gic_intr(void *);
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struct mtk_gic_irqsrc {
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struct intr_irqsrc isrc;
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u_int irq;
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};
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struct mtk_gic_softc {
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device_t gic_dev;
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void * gic_intrhand;
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struct resource * gic_res[2];
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struct mtk_gic_irqsrc gic_irqs[MTK_NIRQS];
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struct mtx mutex;
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uint32_t nirqs;
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};
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#define GIC_INTR_ISRC(sc, irq) (&(sc)->gic_irqs[(irq)].isrc)
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static struct resource_spec mtk_gic_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Registers */
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{ -1, 0 }
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};
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static struct ofw_compat_data compat_data[] = {
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{ "mti,gic", 1 },
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{ NULL, 0 }
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};
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#define READ4(_sc, _reg) bus_read_4((_sc)->gic_res[0], (_reg))
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#define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->gic_res[0], (_reg), (_val))
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static int
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mtk_gic_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "MTK Interrupt Controller (GIC)");
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return (BUS_PROBE_DEFAULT);
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}
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static inline void
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gic_irq_unmask(struct mtk_gic_softc *sc, u_int irq)
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{
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WRITE4(sc, MTK_INTENA, (1u << (irq)));
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}
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static inline void
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gic_irq_mask(struct mtk_gic_softc *sc, u_int irq)
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{
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WRITE4(sc, MTK_INTDIS, (1u << (irq)));
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}
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static inline intptr_t
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gic_xref(device_t dev)
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{
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return (OF_xref_from_node(ofw_bus_get_node(dev)));
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}
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static int
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mtk_gic_register_isrcs(struct mtk_gic_softc *sc)
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{
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int error;
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uint32_t irq;
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struct intr_irqsrc *isrc;
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const char *name;
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name = device_get_nameunit(sc->gic_dev);
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for (irq = 0; irq < sc->nirqs; irq++) {
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sc->gic_irqs[irq].irq = irq;
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isrc = GIC_INTR_ISRC(sc, irq);
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error = intr_isrc_register(isrc, sc->gic_dev, 0, "%s", name);
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if (error != 0) {
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/* XXX call intr_isrc_deregister */
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device_printf(sc->gic_dev, "%s failed", __func__);
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return (error);
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}
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}
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return (0);
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}
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static int
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mtk_gic_attach(device_t dev)
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{
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struct mtk_gic_softc *sc;
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intptr_t xref = gic_xref(dev);
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int i;
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sc = device_get_softc(dev);
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if (bus_alloc_resources(dev, mtk_gic_spec, sc->gic_res)) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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sc->gic_dev = dev;
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/* Initialize mutex */
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mtx_init(&sc->mutex, "PIC lock", "", MTX_SPIN);
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/* Set the number of interrupts */
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sc->nirqs = nitems(sc->gic_irqs);
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/* Mask all interrupts */
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WRITE4(sc, MTK_INTDIS, 0xFFFFFFFF);
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/* All interrupts are of type level */
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WRITE4(sc, MTK_INTTRIG, 0x00000000);
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/* All interrupts are of positive polarity */
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WRITE4(sc, MTK_INTPOL, 0xFFFFFFFF);
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/*
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* Route all interrupts to pin 0 on VPE 0;
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*/
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for (i = 0; i < 32; i++) {
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WRITE4(sc, MTK_MAPPIN(i), MTK_PIN_BITS(0));
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WRITE4(sc, MTK_MAPVPE(i, 0), MTK_VPE_BITS(0));
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}
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/* Register the interrupts */
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if (mtk_gic_register_isrcs(sc) != 0) {
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device_printf(dev, "could not register GIC ISRCs\n");
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goto cleanup;
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}
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/*
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* Now, when everything is initialized, it's right time to
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* register interrupt controller to interrupt framefork.
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*/
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if (intr_pic_register(dev, xref) == NULL) {
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device_printf(dev, "could not register PIC\n");
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goto cleanup;
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}
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cpu_establish_hardintr("gic", mtk_gic_intr, NULL, sc, 0, INTR_TYPE_CLK,
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NULL);
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return (0);
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cleanup:
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bus_release_resources(dev, mtk_gic_spec, sc->gic_res);
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return(ENXIO);
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}
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static int
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mtk_gic_intr(void *arg)
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{
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struct mtk_gic_softc *sc = arg;
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struct thread *td;
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uint32_t i, intr;
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td = curthread;
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/* Workaround: do not inflate intr nesting level */
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td->td_intr_nesting_level--;
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intr = READ4(sc, MTK_INTSTAT) & READ4(sc, MTK_INTMASK);
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while ((i = fls(intr)) != 0) {
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i--;
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intr &= ~(1u << i);
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if (intr_isrc_dispatch(GIC_INTR_ISRC(sc, i),
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curthread->td_intr_frame) != 0) {
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device_printf(sc->gic_dev,
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"Stray interrupt %u detected\n", i);
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gic_irq_mask(sc, i);
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continue;
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}
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}
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KASSERT(i == 0, ("all interrupts handled"));
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td->td_intr_nesting_level++;
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return (FILTER_HANDLED);
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}
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static int
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mtk_gic_map_intr(device_t dev, struct intr_map_data *data,
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struct intr_irqsrc **isrcp)
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{
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#ifdef FDT
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struct intr_map_data_fdt *daf;
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struct mtk_gic_softc *sc;
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if (data->type != INTR_MAP_DATA_FDT)
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return (ENOTSUP);
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sc = device_get_softc(dev);
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daf = (struct intr_map_data_fdt *)data;
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if (daf->ncells != 3 || daf->cells[1] >= sc->nirqs)
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return (EINVAL);
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*isrcp = GIC_INTR_ISRC(sc, daf->cells[1]);
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return (0);
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#else
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return (ENOTSUP);
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#endif
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}
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static void
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mtk_gic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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u_int irq;
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irq = ((struct mtk_gic_irqsrc *)isrc)->irq;
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gic_irq_unmask(device_get_softc(dev), irq);
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}
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static void
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mtk_gic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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u_int irq;
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irq = ((struct mtk_gic_irqsrc *)isrc)->irq;
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gic_irq_mask(device_get_softc(dev), irq);
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}
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static void
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mtk_gic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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mtk_gic_disable_intr(dev, isrc);
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}
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static void
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mtk_gic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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mtk_gic_enable_intr(dev, isrc);
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}
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static void
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mtk_gic_post_filter(device_t dev, struct intr_irqsrc *isrc)
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{
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}
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#ifdef SMP
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static int
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mtk_gic_bind(device_t dev, struct intr_irqsrc *isrc)
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{
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return (EOPNOTSUPP);
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}
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static void
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mtk_gic_init_secondary(device_t dev)
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{
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}
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static void
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mtk_gic_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus)
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{
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}
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#endif
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static device_method_t mtk_gic_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, mtk_gic_probe),
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DEVMETHOD(device_attach, mtk_gic_attach),
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/* Interrupt controller interface */
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DEVMETHOD(pic_disable_intr, mtk_gic_disable_intr),
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DEVMETHOD(pic_enable_intr, mtk_gic_enable_intr),
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DEVMETHOD(pic_map_intr, mtk_gic_map_intr),
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DEVMETHOD(pic_post_filter, mtk_gic_post_filter),
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DEVMETHOD(pic_post_ithread, mtk_gic_post_ithread),
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DEVMETHOD(pic_pre_ithread, mtk_gic_pre_ithread),
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#ifdef SMP
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DEVMETHOD(pic_bind, mtk_gic_bind),
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DEVMETHOD(pic_init_secondary, mtk_gic_init_secondary),
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DEVMETHOD(pic_ipi_send, mtk_gic_ipi_send),
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#endif
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{ 0, 0 }
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};
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static driver_t mtk_gic_driver = {
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"intc",
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mtk_gic_methods,
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sizeof(struct mtk_gic_softc),
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};
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static devclass_t mtk_gic_devclass;
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EARLY_DRIVER_MODULE(intc_gic, simplebus, mtk_gic_driver, mtk_gic_devclass, 0, 0,
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BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
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