628 lines
16 KiB
C
628 lines
16 KiB
C
/*-
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* Copyright 2015 John Wehle <john@feith.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Amlogic aml8726 multiprocessor support.
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*
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* Some processors require powering on which involves poking registers
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* on the aobus and cbus ... it's expected that these locations are set
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* in stone.
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*
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* Locking is not used as these routines should only be called by the BP
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* during startup and should complete prior to the APs being released (the
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* issue being to ensure that a register such as AML_SOC_CPU_CLK_CNTL_REG
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* is not concurrently modified).
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/smp.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/cpu.h>
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#include <machine/bus.h>
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#include <machine/smp.h>
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#include <machine/fdt.h>
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#include <machine/intr.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/amlogic/aml8726/aml8726_soc.h>
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static const char *scu_compatible[] = {
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"arm,cortex-a5-scu",
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"arm,cortex-a9-scu",
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NULL
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};
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static const char *scu_errata_764369[] = {
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"arm,cortex-a9-scu",
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NULL
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};
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static const char *cpucfg_compatible[] = {
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"amlogic,aml8726-cpuconfig",
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NULL
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};
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static struct {
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boolean_t errata_764369;
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u_long scu_size;
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struct resource scu_res;
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u_long cpucfg_size;
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struct resource cpucfg_res;
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struct resource aobus_res;
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struct resource cbus_res;
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} aml8726_smp;
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#define AML_SCU_CONTROL_REG 0
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#define AML_SCU_CONTROL_ENABLE 1
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#define AML_SCU_CONFIG_REG 4
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#define AML_SCU_CONFIG_NCPU_MASK 0x3
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#define AML_SCU_CPU_PWR_STATUS_REG 8
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#define AML_SCU_CPU_PWR_STATUS_CPU3_MASK (3 << 24)
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#define AML_SCU_CPU_PWR_STATUS_CPU2_MASK (3 << 16)
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#define AML_SCU_CPU_PWR_STATUS_CPU1_MASK (3 << 8)
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#define AML_SCU_CPU_PWR_STATUS_CPU0_MASK 3
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#define AML_SCU_INV_TAGS_REG 12
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#define AML_SCU_DIAG_CONTROL_REG 48
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#define AML_SCU_DIAG_CONTROL_DISABLE_MIGBIT 1
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#define AML_CPUCONF_CONTROL_REG 0
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#define AML_CPUCONF_CPU1_ADDR_REG 4
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#define AML_CPUCONF_CPU2_ADDR_REG 8
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#define AML_CPUCONF_CPU3_ADDR_REG 12
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/* aobus */
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#define AML_M8_CPU_PWR_CNTL0_REG 0xe0
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#define AML_M8B_CPU_PWR_CNTL0_MODE_CPU3_MASK (3 << 22)
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#define AML_M8B_CPU_PWR_CNTL0_MODE_CPU2_MASK (3 << 20)
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#define AML_M8B_CPU_PWR_CNTL0_MODE_CPU1_MASK (3 << 18)
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#define AML_M8_CPU_PWR_CNTL0_ISO_CPU3 (1 << 3)
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#define AML_M8_CPU_PWR_CNTL0_ISO_CPU2 (1 << 2)
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#define AML_M8_CPU_PWR_CNTL0_ISO_CPU1 (1 << 1)
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#define AML_M8_CPU_PWR_CNTL1_REG 0xe4
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#define AML_M8B_CPU_PWR_CNTL1_PWR_CPU3 (1 << 19)
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#define AML_M8B_CPU_PWR_CNTL1_PWR_CPU2 (1 << 18)
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#define AML_M8B_CPU_PWR_CNTL1_PWR_CPU1 (1 << 17)
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#define AML_M8_CPU_PWR_CNTL1_MODE_CPU3_MASK (3 << 8)
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#define AML_M8_CPU_PWR_CNTL1_MODE_CPU2_MASK (3 << 6)
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#define AML_M8_CPU_PWR_CNTL1_MODE_CPU1_MASK (3 << 4)
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#define AML_M8B_CPU_PWR_MEM_PD0_REG 0xf4
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#define AML_M8B_CPU_PWR_MEM_PD0_CPU3 (0xf << 20)
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#define AML_M8B_CPU_PWR_MEM_PD0_CPU2 (0xf << 24)
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#define AML_M8B_CPU_PWR_MEM_PD0_CPU1 (0xf << 28)
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/* cbus */
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#define AML_SOC_CPU_CLK_CNTL_REG 0x419c
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#define AML_M8_CPU_CLK_CNTL_RESET_CPU3 (1 << 27)
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#define AML_M8_CPU_CLK_CNTL_RESET_CPU2 (1 << 26)
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#define AML_M8_CPU_CLK_CNTL_RESET_CPU1 (1 << 25)
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#define SCU_WRITE_4(reg, value) bus_write_4(&aml8726_smp.scu_res, \
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(reg), (value))
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#define SCU_READ_4(reg) bus_read_4(&aml8726_smp.scu_res, (reg))
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#define SCU_BARRIER(reg) bus_barrier(&aml8726_smp.scu_res, \
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(reg), 4, (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE))
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#define CPUCONF_WRITE_4(reg, value) bus_write_4(&aml8726_smp.cpucfg_res, \
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(reg), (value))
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#define CPUCONF_READ_4(reg) bus_read_4(&aml8726_smp.cpucfg_res, \
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(reg))
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#define CPUCONF_BARRIER(reg) bus_barrier(&aml8726_smp.cpucfg_res, \
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(reg), 4, (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE))
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#define AOBUS_WRITE_4(reg, value) bus_write_4(&aml8726_smp.aobus_res, \
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(reg), (value))
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#define AOBUS_READ_4(reg) bus_read_4(&aml8726_smp.aobus_res, \
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(reg))
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#define AOBUS_BARRIER(reg) bus_barrier(&aml8726_smp.aobus_res, \
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(reg), 4, (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE))
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#define CBUS_WRITE_4(reg, value) bus_write_4(&aml8726_smp.cbus_res, \
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(reg), (value))
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#define CBUS_READ_4(reg) bus_read_4(&aml8726_smp.cbus_res, \
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(reg))
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#define CBUS_BARRIER(reg) bus_barrier(&aml8726_smp.cbus_res, \
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(reg), 4, (BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE))
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static phandle_t
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find_node_for_device(const char *device, const char **compatible)
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{
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int i;
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phandle_t node;
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/*
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* Try to access the node directly i.e. through /aliases/.
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*/
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if ((node = OF_finddevice(device)) != 0)
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for (i = 0; compatible[i]; i++)
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if (fdt_is_compatible_strict(node, compatible[i]))
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return node;
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/*
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* Find the node the long way.
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*/
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for (i = 0; compatible[i]; i++) {
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if ((node = OF_finddevice("/soc")) == 0)
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return (0);
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if ((node = fdt_find_compatible(node, compatible[i], 1)) != 0)
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return node;
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}
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return (0);
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}
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static int
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alloc_resource_for_node(phandle_t node, struct resource *res, u_long *size)
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{
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int err;
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u_long pbase, psize;
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u_long start;
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if ((err = fdt_get_range(OF_parent(node), 0, &pbase, &psize)) != 0 ||
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(err = fdt_regsize(node, &start, size)) != 0)
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return (err);
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start += pbase;
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memset(res, 0, sizeof(*res));
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res->r_bustag = fdtbus_bs_tag;
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err = bus_space_map(res->r_bustag, start, *size, 0, &res->r_bushandle);
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return (err);
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}
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static void
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power_on_cpu(int cpu)
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{
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uint32_t scpsr;
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uint32_t value;
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if (cpu <= 0)
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return;
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/*
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* Power on the CPU if the intricate details are known, otherwise
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* just hope for the best (it may have already be powered on by
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* the hardware / firmware).
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*/
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switch (aml8726_soc_hw_rev) {
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case AML_SOC_HW_REV_M8:
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case AML_SOC_HW_REV_M8B:
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/*
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* Set the SCU power status for the CPU to normal mode.
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*/
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scpsr = SCU_READ_4(AML_SCU_CPU_PWR_STATUS_REG);
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scpsr &= ~(AML_SCU_CPU_PWR_STATUS_CPU1_MASK << ((cpu - 1) * 8));
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SCU_WRITE_4(AML_SCU_CPU_PWR_STATUS_REG, scpsr);
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SCU_BARRIER(AML_SCU_CPU_PWR_STATUS_REG);
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if (aml8726_soc_hw_rev == AML_SOC_HW_REV_M8B) {
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/*
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* Reset may cause the current power status from the
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* actual CPU to be written to the SCU (over-writing
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* the value we've just written) so set it to normal
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* mode as well.
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*/
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value = AOBUS_READ_4(AML_M8_CPU_PWR_CNTL0_REG);
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value &= ~(AML_M8B_CPU_PWR_CNTL0_MODE_CPU1_MASK <<
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((cpu - 1) * 2));
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AOBUS_WRITE_4(AML_M8_CPU_PWR_CNTL0_REG, value);
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AOBUS_BARRIER(AML_M8_CPU_PWR_CNTL0_REG);
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}
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DELAY(5);
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/*
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* Assert reset.
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*/
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value = CBUS_READ_4(AML_SOC_CPU_CLK_CNTL_REG);
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value |= AML_M8_CPU_CLK_CNTL_RESET_CPU1 << (cpu - 1);
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CBUS_WRITE_4(AML_SOC_CPU_CLK_CNTL_REG, value);
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CBUS_BARRIER(AML_SOC_CPU_CLK_CNTL_REG);
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if (aml8726_soc_hw_rev == AML_SOC_HW_REV_M8B) {
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/*
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* Release RAM pull-down.
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*/
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value = AOBUS_READ_4(AML_M8B_CPU_PWR_MEM_PD0_REG);
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value &= ~((uint32_t)AML_M8B_CPU_PWR_MEM_PD0_CPU1 >>
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((cpu - 1) * 4));
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AOBUS_WRITE_4(AML_M8B_CPU_PWR_MEM_PD0_REG, value);
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AOBUS_BARRIER(AML_M8B_CPU_PWR_MEM_PD0_REG);
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}
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/*
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* Power on CPU.
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*/
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value = AOBUS_READ_4(AML_M8_CPU_PWR_CNTL1_REG);
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value &= ~(AML_M8_CPU_PWR_CNTL1_MODE_CPU1_MASK <<
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((cpu - 1) * 2));
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AOBUS_WRITE_4(AML_M8_CPU_PWR_CNTL1_REG, value);
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AOBUS_BARRIER(AML_M8_CPU_PWR_CNTL1_REG);
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DELAY(10);
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if (aml8726_soc_hw_rev == AML_SOC_HW_REV_M8B) {
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/*
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* Wait for power on confirmation.
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*/
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for ( ; ; ) {
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value = AOBUS_READ_4(AML_M8_CPU_PWR_CNTL1_REG);
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value &= AML_M8B_CPU_PWR_CNTL1_PWR_CPU1 <<
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(cpu - 1);
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if (value)
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break;
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DELAY(10);
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}
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}
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/*
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* Release peripheral clamp.
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*/
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value = AOBUS_READ_4(AML_M8_CPU_PWR_CNTL0_REG);
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value &= ~(AML_M8_CPU_PWR_CNTL0_ISO_CPU1 << (cpu - 1));
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AOBUS_WRITE_4(AML_M8_CPU_PWR_CNTL0_REG, value);
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AOBUS_BARRIER(AML_M8_CPU_PWR_CNTL0_REG);
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/*
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* Release reset.
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*/
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value = CBUS_READ_4(AML_SOC_CPU_CLK_CNTL_REG);
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value &= ~(AML_M8_CPU_CLK_CNTL_RESET_CPU1 << (cpu - 1));
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CBUS_WRITE_4(AML_SOC_CPU_CLK_CNTL_REG, value);
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CBUS_BARRIER(AML_SOC_CPU_CLK_CNTL_REG);
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if (aml8726_soc_hw_rev == AML_SOC_HW_REV_M8B) {
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/*
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* The Amlogic Linux platform code sets the SCU power
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* status for the CPU again for some reason so we
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* follow suit (perhaps in case the reset caused
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* a stale power status from the actual CPU to be
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* written to the SCU).
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*/
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SCU_WRITE_4(AML_SCU_CPU_PWR_STATUS_REG, scpsr);
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SCU_BARRIER(AML_SCU_CPU_PWR_STATUS_REG);
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}
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break;
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default:
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break;
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}
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}
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void
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platform_mp_setmaxid(void)
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{
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int err;
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int i;
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int ncpu;
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phandle_t cpucfg_node;
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phandle_t scu_node;
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uint32_t value;
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if (mp_ncpus != 0)
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return;
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ncpu = 1;
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/*
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* Is the hardware necessary for SMP present?
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*/
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if ((scu_node = find_node_for_device("scu", scu_compatible)) == 0)
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goto moveon;
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if ((cpucfg_node = find_node_for_device("cpuconfig",
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cpucfg_compatible)) == 0)
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goto moveon;
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if (alloc_resource_for_node(scu_node, &aml8726_smp.scu_res,
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&aml8726_smp.scu_size) != 0)
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panic("Could not allocate resource for SCU");
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if (alloc_resource_for_node(cpucfg_node, &aml8726_smp.cpucfg_res,
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&aml8726_smp.cpucfg_size) != 0)
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panic("Could not allocate resource for CPUCONFIG");
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/*
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* Strictly speaking the aobus and cbus may not be required in
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* order to start an AP (it depends on the processor), however
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* always mapping them in simplifies the code.
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*/
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aml8726_smp.aobus_res.r_bustag = fdtbus_bs_tag;
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err = bus_space_map(aml8726_smp.aobus_res.r_bustag,
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AML_SOC_AOBUS_BASE_ADDR, 0x100000,
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0, &aml8726_smp.aobus_res.r_bushandle);
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if (err)
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panic("Could not allocate resource for AOBUS");
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aml8726_smp.cbus_res.r_bustag = fdtbus_bs_tag;
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err = bus_space_map(aml8726_smp.cbus_res.r_bustag,
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AML_SOC_CBUS_BASE_ADDR, 0x100000,
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0, &aml8726_smp.cbus_res.r_bushandle);
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if (err)
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panic("Could not allocate resource for CBUS");
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aml8726_smp.errata_764369 = false;
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for (i = 0; scu_errata_764369[i]; i++)
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if (fdt_is_compatible_strict(scu_node, scu_errata_764369[i])) {
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aml8726_smp.errata_764369 = true;
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break;
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}
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/*
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* Read the number of CPUs present.
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*/
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value = SCU_READ_4(AML_SCU_CONFIG_REG);
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ncpu = (value & AML_SCU_CONFIG_NCPU_MASK) + 1;
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moveon:
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mp_ncpus = ncpu;
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mp_maxid = ncpu - 1;
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}
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void
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platform_mp_start_ap(void)
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{
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int i;
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uint32_t reg;
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uint32_t value;
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vm_paddr_t paddr;
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if (mp_ncpus < 2)
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return;
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/*
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* Invalidate SCU cache tags. The 0x0000ffff constant invalidates
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* all ways on all cores 0-3. Per the ARM docs, it's harmless to
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* write to the bits for cores that are not present.
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*/
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SCU_WRITE_4(AML_SCU_INV_TAGS_REG, 0x0000ffff);
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if (aml8726_smp.errata_764369) {
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/*
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* Erratum ARM/MP: 764369 (problems with cache maintenance).
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* Setting the "disable-migratory bit" in the undocumented SCU
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* Diagnostic Control Register helps work around the problem.
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*/
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value = SCU_READ_4(AML_SCU_DIAG_CONTROL_REG);
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value |= AML_SCU_DIAG_CONTROL_DISABLE_MIGBIT;
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SCU_WRITE_4(AML_SCU_DIAG_CONTROL_REG, value);
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}
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/*
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* Enable the SCU, then clean the cache on this core. After these
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* two operations the cache tag ram in the SCU is coherent with
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* the contents of the cache on this core. The other cores aren't
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* running yet so their caches can't contain valid data yet, however
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* we've initialized their SCU tag ram above, so they will be
|
|
* coherent from startup.
|
|
*/
|
|
value = SCU_READ_4(AML_SCU_CONTROL_REG);
|
|
value |= AML_SCU_CONTROL_ENABLE;
|
|
SCU_WRITE_4(AML_SCU_CONTROL_REG, value);
|
|
SCU_BARRIER(AML_SCU_CONTROL_REG);
|
|
dcache_wbinv_poc_all();
|
|
|
|
/* Set the boot address and power on each AP. */
|
|
paddr = pmap_kextract((vm_offset_t)mpentry);
|
|
for (i = 1; i < mp_ncpus; i++) {
|
|
reg = AML_CPUCONF_CPU1_ADDR_REG + ((i - 1) * 4);
|
|
CPUCONF_WRITE_4(reg, paddr);
|
|
CPUCONF_BARRIER(reg);
|
|
|
|
power_on_cpu(i);
|
|
}
|
|
|
|
/*
|
|
* Enable the APs.
|
|
*
|
|
* The Amlogic Linux platform code sets the lsb for some reason
|
|
* in addition to the enable bit for each AP so we follow suit
|
|
* (the lsb may be the enable bit for the BP, though in that case
|
|
* it should already be set since it's currently running).
|
|
*/
|
|
value = CPUCONF_READ_4(AML_CPUCONF_CONTROL_REG);
|
|
value |= 1;
|
|
for (i = 1; i < mp_ncpus; i++)
|
|
value |= (1 << i);
|
|
CPUCONF_WRITE_4(AML_CPUCONF_CONTROL_REG, value);
|
|
CPUCONF_BARRIER(AML_CPUCONF_CONTROL_REG);
|
|
|
|
/* Wakeup the now enabled APs */
|
|
armv7_sev();
|
|
|
|
/*
|
|
* Free the resources which are not needed after startup.
|
|
*/
|
|
bus_space_unmap(aml8726_smp.scu_res.r_bustag,
|
|
aml8726_smp.scu_res.r_bushandle,
|
|
aml8726_smp.scu_size);
|
|
bus_space_unmap(aml8726_smp.cpucfg_res.r_bustag,
|
|
aml8726_smp.cpucfg_res.r_bushandle,
|
|
aml8726_smp.cpucfg_size);
|
|
bus_space_unmap(aml8726_smp.aobus_res.r_bustag,
|
|
aml8726_smp.aobus_res.r_bushandle,
|
|
0x100000);
|
|
bus_space_unmap(aml8726_smp.cbus_res.r_bustag,
|
|
aml8726_smp.cbus_res.r_bushandle,
|
|
0x100000);
|
|
memset(&aml8726_smp, 0, sizeof(aml8726_smp));
|
|
}
|
|
|
|
/*
|
|
* Stub drivers for cosmetic purposes.
|
|
*/
|
|
struct aml8726_scu_softc {
|
|
device_t dev;
|
|
};
|
|
|
|
static int
|
|
aml8726_scu_probe(device_t dev)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; scu_compatible[i]; i++)
|
|
if (ofw_bus_is_compatible(dev, scu_compatible[i]))
|
|
break;
|
|
|
|
if (!scu_compatible[i])
|
|
return (ENXIO);
|
|
|
|
device_set_desc(dev, "ARM Snoop Control Unit");
|
|
|
|
return (BUS_PROBE_DEFAULT);
|
|
}
|
|
|
|
static int
|
|
aml8726_scu_attach(device_t dev)
|
|
{
|
|
struct aml8726_scu_softc *sc = device_get_softc(dev);
|
|
|
|
sc->dev = dev;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
aml8726_scu_detach(device_t dev)
|
|
{
|
|
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t aml8726_scu_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, aml8726_scu_probe),
|
|
DEVMETHOD(device_attach, aml8726_scu_attach),
|
|
DEVMETHOD(device_detach, aml8726_scu_detach),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t aml8726_scu_driver = {
|
|
"scu",
|
|
aml8726_scu_methods,
|
|
sizeof(struct aml8726_scu_softc),
|
|
};
|
|
|
|
static devclass_t aml8726_scu_devclass;
|
|
|
|
EARLY_DRIVER_MODULE(scu, simplebus, aml8726_scu_driver, aml8726_scu_devclass,
|
|
0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_MIDDLE);
|
|
|
|
struct aml8726_cpucfg_softc {
|
|
device_t dev;
|
|
};
|
|
|
|
static int
|
|
aml8726_cpucfg_probe(device_t dev)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; cpucfg_compatible[i]; i++)
|
|
if (ofw_bus_is_compatible(dev, cpucfg_compatible[i]))
|
|
break;
|
|
|
|
if (!cpucfg_compatible[i])
|
|
return (ENXIO);
|
|
|
|
device_set_desc(dev, "Amlogic CPU Config");
|
|
|
|
return (BUS_PROBE_DEFAULT);
|
|
}
|
|
|
|
static int
|
|
aml8726_cpucfg_attach(device_t dev)
|
|
{
|
|
struct aml8726_cpucfg_softc *sc = device_get_softc(dev);
|
|
|
|
sc->dev = dev;
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
aml8726_cpucfg_detach(device_t dev)
|
|
{
|
|
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t aml8726_cpucfg_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, aml8726_cpucfg_probe),
|
|
DEVMETHOD(device_attach, aml8726_cpucfg_attach),
|
|
DEVMETHOD(device_detach, aml8726_cpucfg_detach),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t aml8726_cpucfg_driver = {
|
|
"cpuconfig",
|
|
aml8726_cpucfg_methods,
|
|
sizeof(struct aml8726_cpucfg_softc),
|
|
};
|
|
|
|
static devclass_t aml8726_cpucfg_devclass;
|
|
|
|
EARLY_DRIVER_MODULE(cpuconfig, simplebus, aml8726_cpucfg_driver,
|
|
aml8726_cpucfg_devclass, 0, 0, BUS_PASS_CPU + BUS_PASS_ORDER_MIDDLE);
|