544 lines
14 KiB
C
544 lines
14 KiB
C
/*-
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* Copyright (c) 2012 Damjan Marion <dmarion@Freebsd.org>
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* All rights reserved.
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*
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* Based on OMAP3 INTC code by Ben Gray
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/ktr.h>
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#include <sys/module.h>
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#include <sys/proc.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#ifdef SOC_BCM2836
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#include <arm/broadcom/bcm2835/bcm2836.h>
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#endif
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#ifdef INTRNG
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#include "pic_if.h"
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#endif
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#define INTC_PENDING_BASIC 0x00
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#define INTC_PENDING_BANK1 0x04
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#define INTC_PENDING_BANK2 0x08
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#define INTC_FIQ_CONTROL 0x0C
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#define INTC_ENABLE_BANK1 0x10
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#define INTC_ENABLE_BANK2 0x14
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#define INTC_ENABLE_BASIC 0x18
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#define INTC_DISABLE_BANK1 0x1C
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#define INTC_DISABLE_BANK2 0x20
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#define INTC_DISABLE_BASIC 0x24
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#define INTC_PENDING_BASIC_ARM 0x0000FF
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#define INTC_PENDING_BASIC_GPU1_PEND 0x000100
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#define INTC_PENDING_BASIC_GPU2_PEND 0x000200
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#define INTC_PENDING_BASIC_GPU1_7 0x000400
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#define INTC_PENDING_BASIC_GPU1_9 0x000800
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#define INTC_PENDING_BASIC_GPU1_10 0x001000
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#define INTC_PENDING_BASIC_GPU1_18 0x002000
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#define INTC_PENDING_BASIC_GPU1_19 0x004000
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#define INTC_PENDING_BASIC_GPU2_21 0x008000
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#define INTC_PENDING_BASIC_GPU2_22 0x010000
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#define INTC_PENDING_BASIC_GPU2_23 0x020000
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#define INTC_PENDING_BASIC_GPU2_24 0x040000
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#define INTC_PENDING_BASIC_GPU2_25 0x080000
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#define INTC_PENDING_BASIC_GPU2_30 0x100000
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#define INTC_PENDING_BASIC_MASK 0x1FFFFF
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#define INTC_PENDING_BASIC_GPU1_MASK (INTC_PENDING_BASIC_GPU1_7 | \
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INTC_PENDING_BASIC_GPU1_9 | \
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INTC_PENDING_BASIC_GPU1_10 | \
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INTC_PENDING_BASIC_GPU1_18 | \
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INTC_PENDING_BASIC_GPU1_19)
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#define INTC_PENDING_BASIC_GPU2_MASK (INTC_PENDING_BASIC_GPU2_21 | \
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INTC_PENDING_BASIC_GPU2_22 | \
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INTC_PENDING_BASIC_GPU2_23 | \
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INTC_PENDING_BASIC_GPU2_24 | \
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INTC_PENDING_BASIC_GPU2_25 | \
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INTC_PENDING_BASIC_GPU2_30)
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#define INTC_PENDING_BANK1_MASK (~((1 << 7) | (1 << 9) | (1 << 10) | \
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(1 << 18) | (1 << 19)))
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#define INTC_PENDING_BANK2_MASK (~((1 << 21) | (1 << 22) | (1 << 23) | \
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(1 << 24) | (1 << 25) | (1 << 30)))
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#define BANK1_START 8
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#define BANK1_END (BANK1_START + 32 - 1)
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#define BANK2_START (BANK1_START + 32)
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#define BANK2_END (BANK2_START + 32 - 1)
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#ifndef INTRNG
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#define BANK3_START (BANK2_START + 32)
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#define BANK3_END (BANK3_START + 32 - 1)
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#endif
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#define IS_IRQ_BASIC(n) (((n) >= 0) && ((n) < BANK1_START))
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#define IS_IRQ_BANK1(n) (((n) >= BANK1_START) && ((n) <= BANK1_END))
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#define IS_IRQ_BANK2(n) (((n) >= BANK2_START) && ((n) <= BANK2_END))
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#ifndef INTRNG
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#define ID_IRQ_BCM2836(n) (((n) >= BANK3_START) && ((n) <= BANK3_END))
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#endif
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#define IRQ_BANK1(n) ((n) - BANK1_START)
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#define IRQ_BANK2(n) ((n) - BANK2_START)
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#ifdef DEBUG
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#define dprintf(fmt, args...) printf(fmt, ##args)
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#else
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#define dprintf(fmt, args...)
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#endif
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#ifdef INTRNG
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#define BCM_INTC_NIRQS 72 /* 8 + 32 + 32 */
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struct bcm_intc_irqsrc {
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struct intr_irqsrc bii_isrc;
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u_int bii_irq;
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uint16_t bii_disable_reg;
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uint16_t bii_enable_reg;
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uint32_t bii_mask;
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};
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#endif
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struct bcm_intc_softc {
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device_t sc_dev;
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struct resource * intc_res;
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bus_space_tag_t intc_bst;
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bus_space_handle_t intc_bsh;
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#ifdef INTRNG
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struct resource * intc_irq_res;
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void * intc_irq_hdl;
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struct bcm_intc_irqsrc intc_isrcs[BCM_INTC_NIRQS];
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#endif
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};
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static struct bcm_intc_softc *bcm_intc_sc = NULL;
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#define intc_read_4(_sc, reg) \
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bus_space_read_4((_sc)->intc_bst, (_sc)->intc_bsh, (reg))
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#define intc_write_4(_sc, reg, val) \
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bus_space_write_4((_sc)->intc_bst, (_sc)->intc_bsh, (reg), (val))
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#ifdef INTRNG
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static inline void
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bcm_intc_isrc_mask(struct bcm_intc_softc *sc, struct bcm_intc_irqsrc *bii)
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{
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intc_write_4(sc, bii->bii_disable_reg, bii->bii_mask);
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}
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static inline void
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bcm_intc_isrc_unmask(struct bcm_intc_softc *sc, struct bcm_intc_irqsrc *bii)
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{
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intc_write_4(sc, bii->bii_enable_reg, bii->bii_mask);
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}
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static inline int
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bcm2835_intc_active_intr(struct bcm_intc_softc *sc)
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{
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uint32_t pending, pending_gpu;
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pending = intc_read_4(sc, INTC_PENDING_BASIC) & INTC_PENDING_BASIC_MASK;
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if (pending == 0)
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return (-1);
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if (pending & INTC_PENDING_BASIC_ARM)
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return (ffs(pending) - 1);
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if (pending & INTC_PENDING_BASIC_GPU1_MASK) {
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if (pending & INTC_PENDING_BASIC_GPU1_7)
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return (BANK1_START + 7);
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if (pending & INTC_PENDING_BASIC_GPU1_9)
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return (BANK1_START + 9);
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if (pending & INTC_PENDING_BASIC_GPU1_10)
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return (BANK1_START + 10);
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if (pending & INTC_PENDING_BASIC_GPU1_18)
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return (BANK1_START + 18);
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if (pending & INTC_PENDING_BASIC_GPU1_19)
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return (BANK1_START + 19);
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}
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if (pending & INTC_PENDING_BASIC_GPU2_MASK) {
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if (pending & INTC_PENDING_BASIC_GPU2_21)
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return (BANK2_START + 21);
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if (pending & INTC_PENDING_BASIC_GPU2_22)
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return (BANK2_START + 22);
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if (pending & INTC_PENDING_BASIC_GPU2_23)
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return (BANK2_START + 23);
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if (pending & INTC_PENDING_BASIC_GPU2_24)
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return (BANK2_START + 24);
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if (pending & INTC_PENDING_BASIC_GPU2_25)
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return (BANK2_START + 25);
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if (pending & INTC_PENDING_BASIC_GPU2_30)
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return (BANK2_START + 30);
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}
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if (pending & INTC_PENDING_BASIC_GPU1_PEND) {
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pending_gpu = intc_read_4(sc, INTC_PENDING_BANK1);
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pending_gpu &= INTC_PENDING_BANK1_MASK;
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if (pending_gpu != 0)
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return (BANK1_START + ffs(pending_gpu) - 1);
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}
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if (pending & INTC_PENDING_BASIC_GPU2_PEND) {
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pending_gpu = intc_read_4(sc, INTC_PENDING_BANK2);
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pending_gpu &= INTC_PENDING_BANK2_MASK;
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if (pending_gpu != 0)
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return (BANK2_START + ffs(pending_gpu) - 1);
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}
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return (-1); /* It shouldn't end here, but it's hardware. */
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}
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static int
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bcm2835_intc_intr(void *arg)
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{
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int irq, num;
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struct bcm_intc_softc *sc = arg;
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for (num = 0; ; num++) {
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irq = bcm2835_intc_active_intr(sc);
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if (irq == -1)
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break;
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if (intr_isrc_dispatch(&sc->intc_isrcs[irq].bii_isrc,
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curthread->td_intr_frame) != 0) {
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bcm_intc_isrc_mask(sc, &sc->intc_isrcs[irq]);
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device_printf(sc->sc_dev, "Stray irq %u disabled\n",
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irq);
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}
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arm_irq_memory_barrier(0); /* XXX */
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}
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if (num == 0)
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device_printf(sc->sc_dev, "Spurious interrupt detected\n");
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return (FILTER_HANDLED);
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}
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static void
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bcm_intc_enable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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struct bcm_intc_irqsrc *bii = (struct bcm_intc_irqsrc *)isrc;
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arm_irq_memory_barrier(bii->bii_irq);
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bcm_intc_isrc_unmask(device_get_softc(dev), bii);
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}
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static void
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bcm_intc_disable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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bcm_intc_isrc_mask(device_get_softc(dev),
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(struct bcm_intc_irqsrc *)isrc);
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}
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static int
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bcm_intc_map_intr(device_t dev, struct intr_map_data *data,
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struct intr_irqsrc **isrcp)
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{
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u_int irq;
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struct intr_map_data_fdt *daf;
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struct bcm_intc_softc *sc;
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if (data->type != INTR_MAP_DATA_FDT)
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return (ENOTSUP);
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daf = (struct intr_map_data_fdt *)data;
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if (daf->ncells == 1)
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irq = daf->cells[0];
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else if (daf->ncells == 2)
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irq = daf->cells[0] * 32 + daf->cells[1];
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else
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return (EINVAL);
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if (irq >= BCM_INTC_NIRQS)
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return (EINVAL);
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sc = device_get_softc(dev);
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*isrcp = &sc->intc_isrcs[irq].bii_isrc;
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return (0);
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}
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static void
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bcm_intc_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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bcm_intc_disable_intr(dev, isrc);
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}
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static void
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bcm_intc_post_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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bcm_intc_enable_intr(dev, isrc);
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}
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static void
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bcm_intc_post_filter(device_t dev, struct intr_irqsrc *isrc)
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{
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}
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static int
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bcm_intc_pic_register(struct bcm_intc_softc *sc, intptr_t xref)
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{
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struct bcm_intc_irqsrc *bii;
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int error;
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uint32_t irq;
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const char *name;
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name = device_get_nameunit(sc->sc_dev);
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for (irq = 0; irq < BCM_INTC_NIRQS; irq++) {
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bii = &sc->intc_isrcs[irq];
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bii->bii_irq = irq;
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if (IS_IRQ_BASIC(irq)) {
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bii->bii_disable_reg = INTC_DISABLE_BASIC;
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bii->bii_enable_reg = INTC_ENABLE_BASIC;
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bii->bii_mask = 1 << irq;
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} else if (IS_IRQ_BANK1(irq)) {
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bii->bii_disable_reg = INTC_DISABLE_BANK1;
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bii->bii_enable_reg = INTC_ENABLE_BANK1;
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bii->bii_mask = 1 << IRQ_BANK1(irq);
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} else if (IS_IRQ_BANK2(irq)) {
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bii->bii_disable_reg = INTC_DISABLE_BANK2;
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bii->bii_enable_reg = INTC_ENABLE_BANK2;
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bii->bii_mask = 1 << IRQ_BANK2(irq);
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} else
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return (ENXIO);
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error = intr_isrc_register(&bii->bii_isrc, sc->sc_dev, 0,
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"%s,%u", name, irq);
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if (error != 0)
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return (error);
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}
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if (intr_pic_register(sc->sc_dev, xref) == NULL)
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return (ENXIO);
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return (0);
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}
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#endif
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static int
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bcm_intc_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-armctrl-ic"))
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return (ENXIO);
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device_set_desc(dev, "BCM2835 Interrupt Controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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bcm_intc_attach(device_t dev)
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{
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struct bcm_intc_softc *sc = device_get_softc(dev);
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int rid = 0;
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#ifdef INTRNG
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intptr_t xref;
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#endif
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sc->sc_dev = dev;
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if (bcm_intc_sc)
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return (ENXIO);
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sc->intc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
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if (sc->intc_res == NULL) {
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device_printf(dev, "could not allocate memory resource\n");
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return (ENXIO);
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}
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#ifdef INTRNG
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xref = OF_xref_from_node(ofw_bus_get_node(dev));
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if (bcm_intc_pic_register(sc, xref) != 0) {
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->intc_res);
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device_printf(dev, "could not register PIC\n");
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return (ENXIO);
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}
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rid = 0;
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sc->intc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE);
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if (sc->intc_irq_res == NULL) {
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if (intr_pic_claim_root(dev, xref, bcm2835_intc_intr, sc, 0) != 0) {
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/* XXX clean up */
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device_printf(dev, "could not set PIC as a root\n");
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return (ENXIO);
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}
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} else {
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if (bus_setup_intr(dev, sc->intc_irq_res, INTR_TYPE_CLK,
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bcm2835_intc_intr, NULL, sc, &sc->intc_irq_hdl)) {
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/* XXX clean up */
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device_printf(dev, "could not setup irq handler\n");
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return (ENXIO);
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}
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}
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#endif
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sc->intc_bst = rman_get_bustag(sc->intc_res);
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sc->intc_bsh = rman_get_bushandle(sc->intc_res);
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bcm_intc_sc = sc;
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return (0);
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}
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static device_method_t bcm_intc_methods[] = {
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DEVMETHOD(device_probe, bcm_intc_probe),
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DEVMETHOD(device_attach, bcm_intc_attach),
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#ifdef INTRNG
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DEVMETHOD(pic_disable_intr, bcm_intc_disable_intr),
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DEVMETHOD(pic_enable_intr, bcm_intc_enable_intr),
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DEVMETHOD(pic_map_intr, bcm_intc_map_intr),
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DEVMETHOD(pic_post_filter, bcm_intc_post_filter),
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DEVMETHOD(pic_post_ithread, bcm_intc_post_ithread),
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DEVMETHOD(pic_pre_ithread, bcm_intc_pre_ithread),
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#endif
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{ 0, 0 }
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};
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static driver_t bcm_intc_driver = {
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"intc",
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bcm_intc_methods,
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sizeof(struct bcm_intc_softc),
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};
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static devclass_t bcm_intc_devclass;
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DRIVER_MODULE(intc, simplebus, bcm_intc_driver, bcm_intc_devclass, 0, 0);
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#ifndef INTRNG
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int
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arm_get_next_irq(int last_irq)
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{
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struct bcm_intc_softc *sc = bcm_intc_sc;
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uint32_t pending;
|
|
int32_t irq = last_irq + 1;
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|
#ifdef SOC_BCM2836
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|
int ret;
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|
#endif
|
|
|
|
/* Sanity check */
|
|
if (irq < 0)
|
|
irq = 0;
|
|
|
|
#ifdef SOC_BCM2836
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|
if ((ret = bcm2836_get_next_irq(irq)) < 0)
|
|
return (-1);
|
|
if (ret != BCM2836_GPU_IRQ)
|
|
return (ret + BANK3_START);
|
|
#endif
|
|
|
|
/* TODO: should we mask last_irq? */
|
|
if (irq < BANK1_START) {
|
|
pending = intc_read_4(sc, INTC_PENDING_BASIC);
|
|
if ((pending & 0xFF) == 0) {
|
|
irq = BANK1_START; /* skip to next bank */
|
|
} else do {
|
|
if (pending & (1 << irq))
|
|
return irq;
|
|
irq++;
|
|
} while (irq < BANK1_START);
|
|
}
|
|
if (irq < BANK2_START) {
|
|
pending = intc_read_4(sc, INTC_PENDING_BANK1);
|
|
if (pending == 0) {
|
|
irq = BANK2_START; /* skip to next bank */
|
|
} else do {
|
|
if (pending & (1 << IRQ_BANK1(irq)))
|
|
return irq;
|
|
irq++;
|
|
} while (irq < BANK2_START);
|
|
}
|
|
if (irq < BANK3_START) {
|
|
pending = intc_read_4(sc, INTC_PENDING_BANK2);
|
|
if (pending != 0) do {
|
|
if (pending & (1 << IRQ_BANK2(irq)))
|
|
return irq;
|
|
irq++;
|
|
} while (irq < BANK3_START);
|
|
}
|
|
return (-1);
|
|
}
|
|
|
|
void
|
|
arm_mask_irq(uintptr_t nb)
|
|
{
|
|
struct bcm_intc_softc *sc = bcm_intc_sc;
|
|
dprintf("%s: %d\n", __func__, nb);
|
|
|
|
if (IS_IRQ_BASIC(nb))
|
|
intc_write_4(sc, INTC_DISABLE_BASIC, (1 << nb));
|
|
else if (IS_IRQ_BANK1(nb))
|
|
intc_write_4(sc, INTC_DISABLE_BANK1, (1 << IRQ_BANK1(nb)));
|
|
else if (IS_IRQ_BANK2(nb))
|
|
intc_write_4(sc, INTC_DISABLE_BANK2, (1 << IRQ_BANK2(nb)));
|
|
#ifdef SOC_BCM2836
|
|
else if (ID_IRQ_BCM2836(nb))
|
|
bcm2836_mask_irq(nb - BANK3_START);
|
|
#endif
|
|
else
|
|
printf("arm_mask_irq: Invalid IRQ number: %d\n", nb);
|
|
}
|
|
|
|
void
|
|
arm_unmask_irq(uintptr_t nb)
|
|
{
|
|
struct bcm_intc_softc *sc = bcm_intc_sc;
|
|
dprintf("%s: %d\n", __func__, nb);
|
|
|
|
if (IS_IRQ_BASIC(nb))
|
|
intc_write_4(sc, INTC_ENABLE_BASIC, (1 << nb));
|
|
else if (IS_IRQ_BANK1(nb))
|
|
intc_write_4(sc, INTC_ENABLE_BANK1, (1 << IRQ_BANK1(nb)));
|
|
else if (IS_IRQ_BANK2(nb))
|
|
intc_write_4(sc, INTC_ENABLE_BANK2, (1 << IRQ_BANK2(nb)));
|
|
#ifdef SOC_BCM2836
|
|
else if (ID_IRQ_BCM2836(nb))
|
|
bcm2836_unmask_irq(nb - BANK3_START);
|
|
#endif
|
|
else
|
|
printf("arm_mask_irq: Invalid IRQ number: %d\n", nb);
|
|
}
|
|
|
|
#ifdef SMP
|
|
void
|
|
intr_pic_init_secondary(void)
|
|
{
|
|
}
|
|
#endif
|
|
#endif
|