117 lines
3.9 KiB
C
117 lines
3.9 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2012 Cavium Inc. (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Inc. nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* cvmx-spx0-defs.h
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*
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* Configuration and status register (CSR) type definitions for
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* Octeon spx0.
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*
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* This file is auto generated. Do not edit.
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*
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* <hr>$Revision$<hr>
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*
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*/
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#ifndef __CVMX_SPX0_DEFS_H__
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#define __CVMX_SPX0_DEFS_H__
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_SPX0_PLL_BW_CTL CVMX_SPX0_PLL_BW_CTL_FUNC()
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static inline uint64_t CVMX_SPX0_PLL_BW_CTL_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN38XX)))
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cvmx_warn("CVMX_SPX0_PLL_BW_CTL not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180090000388ull);
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}
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#else
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#define CVMX_SPX0_PLL_BW_CTL (CVMX_ADD_IO_SEG(0x0001180090000388ull))
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#endif
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#if CVMX_ENABLE_CSR_ADDRESS_CHECKING
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#define CVMX_SPX0_PLL_SETTING CVMX_SPX0_PLL_SETTING_FUNC()
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static inline uint64_t CVMX_SPX0_PLL_SETTING_FUNC(void)
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{
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if (!(OCTEON_IS_MODEL(OCTEON_CN38XX)))
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cvmx_warn("CVMX_SPX0_PLL_SETTING not supported on this chip\n");
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return CVMX_ADD_IO_SEG(0x0001180090000380ull);
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}
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#else
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#define CVMX_SPX0_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180090000380ull))
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#endif
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/**
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* cvmx_spx0_pll_bw_ctl
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*/
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union cvmx_spx0_pll_bw_ctl {
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uint64_t u64;
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struct cvmx_spx0_pll_bw_ctl_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_5_63 : 59;
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uint64_t bw_ctl : 5; /**< Core PLL bandwidth control */
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#else
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uint64_t bw_ctl : 5;
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uint64_t reserved_5_63 : 59;
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#endif
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} s;
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struct cvmx_spx0_pll_bw_ctl_s cn38xx;
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struct cvmx_spx0_pll_bw_ctl_s cn38xxp2;
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};
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typedef union cvmx_spx0_pll_bw_ctl cvmx_spx0_pll_bw_ctl_t;
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/**
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* cvmx_spx0_pll_setting
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*/
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union cvmx_spx0_pll_setting {
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uint64_t u64;
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struct cvmx_spx0_pll_setting_s {
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#ifdef __BIG_ENDIAN_BITFIELD
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uint64_t reserved_17_63 : 47;
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uint64_t setting : 17; /**< Core PLL setting */
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#else
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uint64_t setting : 17;
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uint64_t reserved_17_63 : 47;
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#endif
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} s;
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struct cvmx_spx0_pll_setting_s cn38xx;
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struct cvmx_spx0_pll_setting_s cn38xxp2;
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};
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typedef union cvmx_spx0_pll_setting cvmx_spx0_pll_setting_t;
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#endif
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