679 lines
18 KiB
C
679 lines
18 KiB
C
/* $NetBSD: if_admswreg.h,v 1.1 2007/03/20 08:52:02 dyoung Exp $ */
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/*-
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* Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* 3. The names of the authors may not be used to endorse or promote
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* products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _IF_ADMSWREG_H_
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#define _IF_ADMSWREG_H_
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#define ADMSW_BOOT_DONE 0x0008
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#define ADMSW_BOOT_DONE_BO __BIT(0)
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#define ADMSW_SW_RES 0x000c
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#define ADMSW_SW_RES_SWR __BITS(31, 0)
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#define ADMSW_INT_ST 0x00b0
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#define ADMSW_INT_MASK 0x00b4
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#define ADMSW_INTR_RSVD __BITS(31, 25)
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#define ADMSW_INTR_CPUH __BIT(24)
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#define ADMSW_INTR_SDE __BIT(23)
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#define ADMSW_INTR_RDE __BIT(22)
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#define ADMSW_INTR_W1TE __BIT(21)
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#define ADMSW_INTR_W0TE __BIT(20)
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#define ADMSW_INTR_MI __BIT(19)
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#define ADMSW_INTR_PSC __BIT(18)
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#define ADMSW_INTR_BCS __BIT(16)
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#define ADMSW_INTR_MD __BIT(15)
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#define ADMSW_INTR_GQF __BIT(14)
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#define ADMSW_INTR_CPQ __BIT(13)
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#define ADMSW_INTR_P5QF __BIT(11)
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#define ADMSW_INTR_P4QF __BIT(10)
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#define ADMSW_INTR_P3QF __BIT(9)
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#define ADMSW_INTR_P2QF __BIT(8)
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#define ADMSW_INTR_P1QF __BIT(7)
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#define ADMSW_INTR_P0QF __BIT(6)
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#define ADMSW_INTR_LDF __BIT(5)
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#define ADMSW_INTR_HDF __BIT(4)
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#define ADMSW_INTR_RLD __BIT(3)
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#define ADMSW_INTR_RHD __BIT(2)
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#define ADMSW_INTR_SLD __BIT(1)
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#define ADMSW_INTR_SHD __BIT(0)
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#define ADMSW_INT_FMT \
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"\x10"\
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"\x01SHD"\
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"\x02SLD"\
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"\x03RHD"\
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"\x04RLD"\
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"\x05HDF"\
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"\x06LDF"\
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"\x07P0QF"\
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"\x08P1QF"\
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"\x09P2QF"\
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"\x0aP3QF"\
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"\x0bP4QF"\
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"\x0cP5QF"\
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"\x0e"\
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"CPQ"\
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"\x0fGQF"\
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"\x10MD"\
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"\x11"\
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"BCS"\
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"\x13PSC"\
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"\x14MI"\
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"\x15W0TE"\
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"\x16W1TE"\
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"\x17RDE"\
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"\x18SDE"\
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"\x19"\
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"CPUH"
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#define CODE_REG 0x0000
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#define SFTREST_REG 0x0004
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#define BOOT_DONE_REG 0x0008
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#define GLOBAL_ST_REG 0x0010
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#define PHY_ST_REG 0x0014
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#define PHY_ST_LINKUP (1 << 0)
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#define PHY_ST_100M (1 << 8)
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#define PHY_ST_FDX (1 << 16)
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#define PORT_ST_REG 0x0018
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#define MEM_CONTROL_REG 0x001C
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#define SW_CONF_REG 0x0020
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#define CPUP_CONF_REG 0x0024
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#define CPUP_CONF_DCPUP 0x00000001
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#define CPUP_CONF_CRCP 0x00000002
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#define CPUP_CONF_BTM 0x00000004
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#define CPUP_CONF_DUNP_SHIFT 9
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#define CPUP_CONF_DUNP_MASK (0x3F << CPUP_CONF_DUNP_SHIFT)
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#define CPUP_CONF_DMCP_SHIFT 16
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#define CPUP_CONF_DMCP_MASK (0x3F << CPUP_CONF_DMCP_SHIFT)
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#define CPUP_CONF_DBCP_SHIFT 24
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#define CPUP_CONF_DBCP_MASK (0x3F << CPUP_CONF_DBCP_SHIFT)
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#define PORT_CONF0_REG 0x0028
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#define PORT_CONF0_DP_MASK 0x0000003F
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#define PORT_CONF0_EMCP_MASK 0x00003F00
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#define PORT_CONF0_EMCP_SHIFT 8
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#define PORT_CONF0_EMBP_MASK 0x003F0000
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#define PORT_CONF0_EMBP_SHIFT 16
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#define PORT_CONF1_REG 0x002C
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#define PORT_CONF2_REG 0x0030
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#define VLAN_G1_REG 0x0040
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#define VLAN_G2_REG 0x0044
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#define SEND_TRIG_REG 0x0048
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#define SRCH_CMD_REG 0x004C
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#define ADDR_ST0_REG 0x0050
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#define ADDR_ST1_REG 0x0054
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#define MAC_WT0_REG 0x0058
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#define MAC_WT0_WRITE 0x00000001
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#define MAC_WT0_WRITE_DONE 0x00000002
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#define MAC_WT0_FILTER_EN 0x00000004
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#define MAC_WT0_VLANID_SHIFT 3
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#define MAC_WT0_VLANID_MASK 0x00000038
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#define MAC_WT0_VLANID_EN 0x00000040
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#define MAC_WT0_PORTMAP_MASK 0x00001F80
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#define MAC_WT0_PORTMAP_SHIFT 7
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#define MAC_WT0_AGE_MASK (0x7 << 13)
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#define MAC_WT0_AGE_STATIC (0x7 << 13)
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#define MAC_WT0_AGE_VALID (0x1 << 13)
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#define MAC_WT0_AGE_EMPTY 0
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#define MAC_WT1_REG 0x005C
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#define BW_CNTL0_REG 0x0060
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#define BW_CNTL1_REG 0x0064
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#define PHY_CNTL0_REG 0x0068
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#define PHY_CNTL1_REG 0x006C
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#define FC_TH_REG 0x0070
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#define FC_TH_FCS_MASK 0x01FF0000
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#define FC_TH_D2R_MASK 0x0000FF00
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#define FC_TH_D2S_MASK 0x000000FF
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#define ADJ_PORT_TH_REG 0x0074
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#define PORT_TH_REG 0x0078
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#define PHY_CNTL2_REG 0x007C
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#define PHY_CNTL2_AUTONEG (1 << 0)
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#define PHY_CNTL2_ANE_MASK 0x0000001F
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#define PHY_CNTL2_SC_MASK 0x000003E0
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#define PHY_CNTL2_SC_SHIFT 5
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#define PHY_CNTL2_100M (1 << PHY_CNTL2_SC_SHIFT)
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#define PHY_CNTL2_DC_MASK 0x00007C00
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#define PHY_CNTL2_DC_SHIFT 10
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#define PHY_CNTL2_FDX (1 << PHY_CNTL2_DC_SHIFT)
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#define PHY_CNTL2_RFCV_MASK 0x000F8000
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#define PHY_CNTL2_RFCV_SHIFT 15
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#define PHY_CNTL2_PHYR_MASK 0x01F00000
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#define PHY_CNTL2_PHYR_SHIFT 20
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#define PHY_CNTL2_AMDIX_MASK 0x3E000000
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#define PHY_CNTL2_AMDIX_SHIFT 25
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#define PHY_CNTL2_RMAE 0x40000000
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#define PHY_CNTL3_REG 0x0080
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#define PHY_CNTL3_RNT 0x00000400
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#define PRI_CNTL_REG 0x0084
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#define VLAN_PRI_REG 0x0088
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#define TOS_EN_REG 0x008C
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#define TOS_MAP0_REG 0x0090
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#define TOS_MAP1_REG 0x0094
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#define CUSTOM_PRI1_REG 0x0098
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#define CUSTOM_PRI2_REG 0x009C
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#define EMPTY_CNT_REG 0x00A4
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#define PORT_CNT_SEL_REG 0x00A8
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#define PORT_CNT_REG 0x00AC
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#define INT_MASK 0x1FDEFFF
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#define GPIO_CONF0_REG 0x00B8
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#define GPIO_CONF2_REG 0x00BC
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#define SWAP_IN_REG 0x00C8
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#define SWAP_OUT_REG 0x00CC
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#define SEND_HBADDR_REG 0x00D0
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#define SEND_LBADDR_REG 0x00D4
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#define RECV_HBADDR_REG 0x00D8
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#define RECV_LBADDR_REG 0x00DC
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#define SEND_HWADDR_REG 0x00E0
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#define SEND_LWADDR_REG 0x00E4
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#define RECV_HWADDR_REG 0x00E8
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#define RECV_LWADDR_REG 0x00EC
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#define TIMER_INT_REG 0x00F0
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#define TIMER_REG 0x00F4
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#define PORT0_LED_REG 0x0100
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#define PORT1_LED_REG 0x0104
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#define PORT2_LED_REG 0x0108
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#define PORT3_LED_REG 0x010c
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#define PORT4_LED_REG 0x0110
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/* Hardware descriptor format */
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struct admsw_desc {
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volatile uint32_t data;
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volatile uint32_t cntl;
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volatile uint32_t len;
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volatile uint32_t status;
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} __attribute__((__packed__, __aligned__(4)));
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#define ADM5120_DMA_MASK 0x01ffffff
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#define ADM5120_DMA_OWN 0x80000000 /* buffer owner */
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#define ADM5120_DMA_RINGEND 0x10000000 /* Last in DMA ring */
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#define ADM5120_DMA_BUF2ENABLE 0x80000000
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#define ADM5120_DMA_PORTID 0x00007000
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#define ADM5120_DMA_PORTSHIFT 12
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#define ADM5120_DMA_LEN 0x07ff0000
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#define ADM5120_DMA_LENSHIFT 16
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#define ADM5120_DMA_TYPE 0x00000003
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#define ADM5120_DMA_TYPE_IP 0x00000000
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#define ADM5120_DMA_TYPE_PPPOE 0x00000001
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#define ADM5120_DMA_CSUM 0x80000000
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#define ADM5120_DMA_CSUMFAIL 0x00000008
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#define SW_DEVS 6
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#if 0
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/* CODE_REG */
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#define CODE_ID_MASK 0x00FFFF
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#define CODE_ADM5120_ID 0x5120
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#define CODE_REV_MASK 0x0F0000
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#define CODE_REV_SHIFT 16
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#define CODE_REV_ADM5120_0 0x8
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#define CODE_CLK_MASK 0x300000
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#define CODE_CLK_SHIFT 20
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#define CPU_CLK_175MHZ 0x0
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#define CPU_CLK_200MHZ 0x1
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#define CPU_CLK_225MHZ 0x2
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#define CPU_CLK_250MHZ 0x3
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#define CPU_SPEED_175M (175000000/2)
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#define CPU_SPEED_200M (200000000/2)
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#define CPU_SPEED_225M (225000000/2)
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#define CPU_SPEED_250M (250000000/2)
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#define CPU_NAND_BOOT 0x01000000
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#define CPU_DCACHE_2K_WAY (0x1 << 25)
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#define CPU_DCACHE_2WAY (0x1 << 26)
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#define CPU_ICACHE_2K_WAY (0x1 << 27)
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#define CPU_ICACHE_2WAY (0x1 << 28)
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#define CPU_GMII_SUPPORT 0x20000000
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#define CPU_PQFP_MODE (0x1 << 29)
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#define CPU_CACHE_LINE_SIZE 16
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/* SftRest_REG */
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#define SOFTWARE_RESET 0x1
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/* Boot_done_REG */
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#define BOOT_DONE 0x1
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/* SWReset_REG */
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#define SWITCH_RESET 0x1
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/* Global_St_REG */
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#define DATA_BUF_BIST_FAILED (0x1 << 0)
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#define LINK_TAB_BIST_FAILED (0x1 << 1)
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#define MC_TAB_BIST_FAILED (0x1 << 2)
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#define ADDR_TAB_BIST_FAILED (0x1 << 3)
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#define DCACHE_D_FAILED (0x3 << 4)
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#define DCACHE_T_FAILED (0x1 << 6)
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#define ICACHE_D_FAILED (0x3 << 7)
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#define ICACHE_T_FAILED (0x1 << 9)
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#define BIST_FAILED_MASK 0x03FF
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#define ALLMEM_TEST_DONE (0x1 << 10)
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#define SKIP_BLK_CNT_MASK 0x1FF000
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#define SKIP_BLK_CNT_SHIFT 12
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/* PHY_st_REG */
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#define PORT_LINK_MASK 0x0000001F
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#define PORT_MII_LINKFAIL 0x00000020
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#define PORT_SPEED_MASK 0x00001F00
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#define PORT_GMII_SPD_MASK 0x00006000
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#define PORT_GMII_SPD_10M 0
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#define PORT_GMII_SPD_100M 0x00002000
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#define PORT_GMII_SPD_1000M 0x00004000
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#define PORT_DUPLEX_MASK 0x003F0000
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#define PORT_FLOWCTRL_MASK 0x1F000000
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#define PORT_GMII_FLOWCTRL_MASK 0x60000000
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#define PORT_GMII_FC_ON 0x20000000
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#define PORT_GMII_RXFC_ON 0x20000000
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#define PORT_GMII_TXFC_ON 0x40000000
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/* Port_st_REG */
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#define PORT_SECURE_ST_MASK 0x001F
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#define MII_PORT_TXC_ERR 0x0080
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/* Mem_control_REG */
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#define SDRAM_SIZE_4MBYTES 0x0001
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#define SDRAM_SIZE_8MBYTES 0x0002
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#define SDRAM_SIZE_16MBYTES 0x0003
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#define SDRAM_SIZE_64MBYTES 0x0004
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#define SDRAM_SIZE_128MBYTES 0x0005
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#define SDRAM_SIZE_MASK 0x0007
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#define MEMCNTL_SDRAM1_EN (0x1 << 5)
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#define ROM_SIZE_DISABLE 0x0000
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#define ROM_SIZE_512KBYTES 0x0001
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#define ROM_SIZE_1MBYTES 0x0002
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#define ROM_SIZE_2MBYTES 0x0003
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#define ROM_SIZE_4MBYTES 0x0004
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#define ROM_SIZE_8MBYTES 0x0005
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#define ROM_SIZE_MASK 0x0007
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#define ROM0_SIZE_SHIFT 8
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#define ROM1_SIZE_SHIFT 16
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/* SW_conf_REG */
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#define SW_AGE_TIMER_MASK 0x000000F0
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#define SW_AGE_TIMER_DISABLE 0x0
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#define SW_AGE_TIMER_FAST 0x00000080
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#define SW_AGE_TIMER_300SEC 0x00000010
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#define SW_AGE_TIMER_600SEC 0x00000020
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#define SW_AGE_TIMER_1200SEC 0x00000030
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#define SW_AGE_TIMER_2400SEC 0x00000040
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#define SW_AGE_TIMER_4800SEC 0x00000050
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#define SW_AGE_TIMER_9600SEC 0x00000060
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#define SW_AGE_TIMER_19200SEC 0x00000070
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//#define SW_AGE_TIMER_38400SEC 0x00000070
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#define SW_BC_PREV_MASK 0x00000300
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#define SW_BC_PREV_DISABLE 0
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#define SW_BC_PREV_64BC 0x00000100
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#define SW_BC_PREV_48BC 0x00000200
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#define SW_BC_PREV_32BC 0x00000300
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#define SW_MAX_LEN_MASK 0x00000C00
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#define SW_MAX_LEN_1536 0
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#define SW_MAX_LEN_1522 0x00000800
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#define SW_MAX_LEN_1518 0x00000400
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#define SW_DIS_COLABT 0x00001000
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#define SW_HASH_ALG_MASK 0x00006000
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#define SW_HASH_ALG_DIRECT 0
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#define SW_HASH_ALG_XOR48 0x00002000
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#define SW_HASH_ALG_XOR32 0x00004000
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#define SW_DISABLE_BACKOFF_TIMER 0x00008000
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#define SW_BP_NUM_MASK 0x000F0000
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#define SW_BP_NUM_SHIFT 16
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#define SW_BP_MODE_MASK 0x00300000
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#define SW_BP_MODE_DISABLE 0
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#define SW_BP_MODE_JAM 0x00100000
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#define SW_BP_MODE_JAMALL 0x00200000
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#define SW_BP_MODE_CARRIER 0x00300000
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#define SW_RESRV_MC_FILTER 0x00400000
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#define SW_BISR_DISABLE 0x00800000
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#define SW_DIS_MII_WAS_TX 0x01000000
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#define SW_BISS_EN 0x02000000
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#define SW_BISS_TH_MASK 0x0C000000
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#define SW_BISS_TH_SHIFT 26
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#define SW_REQ_LATENCY_MASK 0xF0000000
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#define SW_REQ_LATENCY_SHIFT 28
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/* CPUp_conf_REG */
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#define SW_CPU_PORT_DISABLE 0x00000001
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#define SW_PADING_CRC 0x00000002
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#define SW_BRIDGE_MODE 0x00000004
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#define SW_DIS_UN_SHIFT 9
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#define SW_DIS_UN_MASK (0x3F << SW_DIS_UN_SHIFT)
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#define SW_DIS_MC_SHIFT 16
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#define SW_DIS_MC_MASK (0x3F << SW_DIS_MC_SHIFT)
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#define SW_DIS_BC_SHIFT 24
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#define SW_DIS_BC_MASK (0x3F << SW_DIS_BC_SHIFT)
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/* Port_conf0_REG */
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#define SW_DISABLE_PORT_MASK 0x0000003F
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#define SW_EN_MC_MASK 0x00003F00
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#define SW_EN_MC_SHIFT 8
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#define SW_EN_BP_MASK 0x003F0000
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#define SW_EN_BP_SHIFT 16
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#define SW_EN_FC_MASK 0x3F000000
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#define SW_EN_FC_SHIFT 24
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/* Port_conf1_REG */
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#define SW_DIS_SA_LEARN_MASK 0x0000003F
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#define SW_PORT_BLOCKING_MASK 0x00000FC0
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#define SW_PORT_BLOCKING_SHIFT 6
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#define SW_PORT_BLOCKING_ON 0x1
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#define SW_PORT_BLOCKING_MODE_MASK 0x0003F000
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#define SW_PORT_BLOCKING_MODE_SHIFT 12
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#define SW_PORT_BLOCKING_CTRLONLY 0x1
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#define SW_EN_PORT_AGE_MASK 0x03F00000
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#define SW_EN_PORT_AGE_SHIFT 20
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#define SW_EN_SA_SECURED_MASK 0xFC000000
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#define SW_EN_SA_SECURED_SHIFT 26
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/* Port_conf2_REG */
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#define SW_GMII_AN_EN 0x00000001
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#define SW_GMII_FORCE_SPD_MASK 0x00000006
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#define SW_GMII_FORCE_SPD_10M 0
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#define SW_GMII_FORCE_SPD_100M 0x2
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#define SW_GMII_FORCE_SPD_1000M 0x4
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#define SW_GMII_FORCE_FULL_DUPLEX 0x00000008
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#define SW_GMII_FORCE_RXFC 0x00000010
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#define SW_GMII_FORCE_TXFC 0x00000020
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#define SW_GMII_EN 0x00000040
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#define SW_GMII_REVERSE 0x00000080
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#define SW_GMII_TXC_CHECK_EN 0x00000100
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#define SW_LED_FLASH_TIME_MASK 0x00030000
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#define SW_LED_FLASH_TIME_30MS 0
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#define SW_LED_FLASH_TIME_60MS 0x00010000
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#define SW_LED_FLASH_TIME_240MS 0x00020000
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#define SW_LED_FLASH_TIME_480MS 0x00030000
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/* Send_trig_REG */
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#define SEND_TRIG_LOW 0x0001
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#define SEND_TRIG_HIGH 0x0002
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/* Srch_cmd_REG */
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#define SW_MAC_SEARCH_START 0x000001
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#define SW_MAX_SEARCH_AGAIN 0x000002
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/* MAC_wt0_REG */
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#define SW_MAC_WRITE 0x00000001
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#define SW_MAC_WRITE_DONE 0x00000002
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#define SW_MAC_FILTER_EN 0x00000004
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#define SW_MAC_VLANID_SHIFT 3
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#define SW_MAC_VLANID_MASK 0x00000038
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#define SW_MAC_VLANID_EN 0x00000040
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#define SW_MAC_PORTMAP_MASK 0x00001F80
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#define SW_MAC_PORTMAP_SHIFT 7
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#define SW_MAC_AGE_MASK (0x7 << 13)
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#define SW_MAC_AGE_STATIC (0x7 << 13)
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#define SW_MAC_AGE_VALID (0x1 << 13)
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#define SW_MAC_AGE_EMPTY 0
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/* BW_cntl0_REG */
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#define SW_PORT_TX_NOLIMIT 0
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#define SW_PORT_TX_64K 1
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#define SW_PORT_TX_128K 2
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#define SW_PORT_TX_256K 3
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#define SW_PORT_TX_512K 4
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#define SW_PORT_TX_1M 5
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#define SW_PORT_TX_4M 6
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#define SW_PORT_TX_10MK 7
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/* BW_cntl1_REG */
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#define SW_TRAFFIC_SHAPE_IPG (0x1 << 31)
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/* PHY_cntl0_REG */
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#define SW_PHY_ADDR_MASK 0x0000001F
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#define PHY_ADDR_MAX 0x1f
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#define SW_PHY_REG_ADDR_MASK 0x00001F00
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#define SW_PHY_REG_ADDR_SHIFT 8
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#define PHY_REG_ADDR_MAX 0x1f
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#define SW_PHY_WRITE 0x00002000
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#define SW_PHY_READ 0x00004000
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#define SW_PHY_WDATA_MASK 0xFFFF0000
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#define SW_PHY_WDATA_SHIFT 16
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/* PHY_cntl1_REG */
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#define SW_PHY_WRITE_DONE 0x00000001
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#define SW_PHY_READ_DONE 0x00000002
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#define SW_PHY_RDATA_MASK 0xFFFF0000
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#define SW_PHY_RDATA_SHIFT 16
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/* FC_th_REG */
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/* Adj_port_th_REG */
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/* Port_th_REG */
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/* PHY_cntl2_REG */
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#define SW_PHY_AN_MASK 0x0000001F
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#define SW_PHY_SPD_MASK 0x000003E0
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#define SW_PHY_SPD_SHIFT 5
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#define SW_PHY_DPX_MASK 0x00007C00
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#define SW_PHY_DPX_SHIFT 10
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#define SW_FORCE_FC_MASK 0x000F8000
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#define SW_FORCE_FC_SHIFT 15
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#define SW_PHY_NORMAL_MASK 0x01F00000
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#define SW_PHY_NORMAL_SHIFT 20
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#define SW_PHY_AUTOMDIX_MASK 0x3E000000
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#define SW_PHY_AUTOMDIX_SHIFT 25
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#define SW_PHY_REC_MCCAVERAGE 0x40000000
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/* PHY_cntl3_REG */
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/* Pri_cntl_REG */
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/* VLAN_pri_REG */
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/* TOS_en_REG */
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/* TOS_map0_REG */
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/* TOS_map1_REG */
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/* Custom_pri1_REG */
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/* Custom_pri2_REG */
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/* Empty_cnt_REG */
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/* Port_cnt_sel_REG */
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/* Port_cnt_REG */
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/* SW_Int_st_REG & SW_Int_mask_REG */
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#define SEND_H_DONE_INT 0x0000001
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#define SEND_L_DONE_INT 0x0000002
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#define RX_H_DONE_INT 0x0000004
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#define RX_L_DONE_INT 0x0000008
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#define RX_H_DESC_FULL_INT 0x0000010
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#define RX_L_DESC_FULL_INT 0x0000020
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#define PORT0_QUE_FULL_INT 0x0000040
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#define PORT1_QUE_FULL_INT 0x0000080
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#define PORT2_QUE_FULL_INT 0x0000100
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#define PORT3_QUE_FULL_INT 0x0000200
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#define PORT4_QUE_FULL_INT 0x0000400
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#define PORT5_QUE_FULL_INT 0x0000800
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#define CPU_QUE_FULL_INT 0x0002000
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#define GLOBAL_QUE_FULL_INT 0x0004000
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#define MUST_DROP_INT 0x0008000
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#define BC_STORM_INT 0x0010000
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#define PORT_STATUS_CHANGE_INT 0x0040000
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#define INTRUDER_INT 0x0080000
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#define WATCHDOG0_EXPR_INT 0x0100000
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#define WATCHDOG1_EXPR_INT 0x0200000
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#define RX_DESC_ERR_INT 0x0400000
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#define SEND_DESC_ERR_INT 0x0800000
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#define CPU_HOLD_INT 0x1000000
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#define SWITCH_INT_MASK 0x1FDEFFF
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/* GPIO_conf0_REG */
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#define GPIO0_INPUT_MODE 0x00000001
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#define GPIO1_INPUT_MODE 0x00000002
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#define GPIO2_INPUT_MODE 0x00000004
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#define GPIO3_INPUT_MODE 0x00000008
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#define GPIO4_INPUT_MODE 0x00000010
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#define GPIO5_INPUT_MODE 0x00000020
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#define GPIO6_INPUT_MODE 0x00000040
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#define GPIO7_INPUT_MODE 0x00000080
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#define GPIO0_OUTPUT_MODE 0
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#define GPIO1_OUTPUT_MODE 0
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#define GPIO2_OUTPUT_MODE 0
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#define GPIO3_OUTPUT_MODE 0
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#define GPIO4_OUTPUT_MODE 0
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#define GPIO5_OUTPUT_MODE 0
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#define GPIO6_OUTPUT_MODE 0
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#define GPIO7_OUTPUT_MODE 0
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#define GPIO0_INPUT_MASK 0x00000100
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#define GPIO1_INPUT_MASK 0x00000200
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#define GPIO2_INPUT_MASK 0x00000400
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#define GPIO3_INPUT_MASK 0x00000800
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#define GPIO4_INPUT_MASK 0x00001000
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#define GPIO5_INPUT_MASK 0x00002000
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#define GPIO6_INPUT_MASK 0x00004000
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#define GPIO7_INPUT_MASK 0x00008000
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#define GPIO0_OUTPUT_EN 0x00010000
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#define GPIO1_OUTPUT_EN 0x00020000
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#define GPIO2_OUTPUT_EN 0x00040000
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#define GPIO3_OUTPUT_EN 0x00080000
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#define GPIO4_OUTPUT_EN 0x00100000
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#define GPIO5_OUTPUT_EN 0x00200000
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#define GPIO6_OUTPUT_EN 0x00400000
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#define GPIO7_OUTPUT_EN 0x00800000
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#define GPIO_CONF0_OUTEN_MASK 0x00ff0000
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#define GPIO0_OUTPUT_HI 0x01000000
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#define GPIO1_OUTPUT_HI 0x02000000
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#define GPIO2_OUTPUT_HI 0x04000000
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#define GPIO3_OUTPUT_HI 0x08000000
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#define GPIO4_OUTPUT_HI 0x10000000
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#define GPIO5_OUTPUT_HI 0x20000000
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#define GPIO6_OUTPUT_HI 0x40000000
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#define GPIO7_OUTPUT_HI 0x80000000
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#define GPIO0_OUTPUT_LOW 0
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#define GPIO1_OUTPUT_LOW 0
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#define GPIO2_OUTPUT_LOW 0
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#define GPIO3_OUTPUT_LOW 0
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#define GPIO4_OUTPUT_LOW 0
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#define GPIO5_OUTPUT_LOW 0
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#define GPIO6_OUTPUT_LOW 0
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#define GPIO7_OUTPUT_LOW 0
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/* GPIO_conf2_REG */
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#define EXTIO_WAIT_EN (0x1 << 6)
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#define EXTIO_CS1_INT1_EN (0x1 << 5)
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#define EXTIO_CS0_INT0_EN (0x1 << 4)
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/* Timer_int_REG */
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#define SW_TIMER_INT_DISABLE 0x10000
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#define SW_TIMER_INT 0x1
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/* Timer_REG */
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#define SW_TIMER_EN 0x10000
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#define SW_TIMER_MASK 0xffff
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#define SW_TIMER_10MS_TICKS 0x3D09
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#define SW_TIMER_1MS_TICKS 0x61A
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#define SW_TIMER_100US_TICKS 0x9D
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/* Port0_LED_REG, Port1_LED_REG, Port2_LED_REG, Port3_LED_REG, Port4_LED_REG*/
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#define GPIOL_INPUT_MODE 0x00
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#define GPIOL_OUTPUT_FLASH 0x01
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#define GPIOL_OUTPUT_LOW 0x02
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#define GPIOL_OUTPUT_HIGH 0x03
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#define GPIOL_LINK_LED 0x04
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#define GPIOL_SPEED_LED 0x05
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#define GPIOL_DUPLEX_LED 0x06
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#define GPIOL_ACT_LED 0x07
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#define GPIOL_COL_LED 0x08
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#define GPIOL_LINK_ACT_LED 0x09
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#define GPIOL_DUPLEX_COL_LED 0x0A
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#define GPIOL_10MLINK_ACT_LED 0x0B
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#define GPIOL_100MLINK_ACT_LED 0x0C
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#define GPIOL_CTRL_MASK 0x0F
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#define GPIOL_INPUT_MASK 0x7000
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#define GPIOL_INPUT_0_MASK 0x1000
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#define GPIOL_INPUT_1_MASK 0x2000
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#define GPIOL_INPUT_2_MASK 0x4000
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#define PORT_LED0_SHIFT 0
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#define PORT_LED1_SHIFT 4
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#define PORT_LED2_SHIFT 8
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#endif
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#endif /* _IF_ADMSWREG_H_ */
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