481 lines
11 KiB
C
481 lines
11 KiB
C
/* $NetBSD: uart.c,v 1.2 2007/03/23 20:05:47 dogcow Exp $ */
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/*-
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* Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
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* Copyright (c) 2007 Oleksandr Tymoshenko.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* 3. The names of the authors may not be used to endorse or promote
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* products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <machine/bus.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_cpu.h>
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#include <dev/uart/uart_bus.h>
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#include <mips/adm5120/uart_dev_adm5120.h>
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#include "uart_if.h"
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/*
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* Low-level UART interface.
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*/
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static int adm5120_uart_probe(struct uart_bas *bas);
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static void adm5120_uart_init(struct uart_bas *bas, int, int, int, int);
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static void adm5120_uart_term(struct uart_bas *bas);
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static void adm5120_uart_putc(struct uart_bas *bas, int);
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static int adm5120_uart_rxready(struct uart_bas *bas);
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static int adm5120_uart_getc(struct uart_bas *bas, struct mtx *);
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static struct uart_ops uart_adm5120_uart_ops = {
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.probe = adm5120_uart_probe,
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.init = adm5120_uart_init,
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.term = adm5120_uart_term,
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.putc = adm5120_uart_putc,
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.rxready = adm5120_uart_rxready,
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.getc = adm5120_uart_getc,
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};
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static int
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adm5120_uart_probe(struct uart_bas *bas)
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{
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return (0);
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}
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static void
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adm5120_uart_init(struct uart_bas *bas, int baudrate, int databits,
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int stopbits, int parity)
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{
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/* TODO: Set parameters for uart, meanwhile stick with 115200N1 */
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}
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static void
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adm5120_uart_term(struct uart_bas *bas)
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{
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}
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static void
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adm5120_uart_putc(struct uart_bas *bas, int c)
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{
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char chr;
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chr = c;
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while (uart_getreg(bas, UART_FR_REG) & UART_FR_TX_FIFO_FULL)
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;
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uart_setreg(bas, UART_DR_REG, c);
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while (uart_getreg(bas, UART_FR_REG) & UART_FR_BUSY)
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;
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uart_barrier(bas);
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}
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static int
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adm5120_uart_rxready(struct uart_bas *bas)
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{
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if (uart_getreg(bas, UART_FR_REG) & UART_FR_RX_FIFO_EMPTY)
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return (0);
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return (1);
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}
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static int
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adm5120_uart_getc(struct uart_bas *bas, struct mtx *hwmtx)
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{
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int c;
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uart_lock(hwmtx);
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while (uart_getreg(bas, UART_FR_REG) & UART_FR_RX_FIFO_EMPTY) {
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uart_unlock(hwmtx);
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DELAY(10);
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uart_lock(hwmtx);
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}
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c = uart_getreg(bas, UART_DR_REG);
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uart_unlock(hwmtx);
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return (c);
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}
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/*
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* High-level UART interface.
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*/
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struct adm5120_uart_softc {
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struct uart_softc base;
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};
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static int adm5120_uart_bus_attach(struct uart_softc *);
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static int adm5120_uart_bus_detach(struct uart_softc *);
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static int adm5120_uart_bus_flush(struct uart_softc *, int);
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static int adm5120_uart_bus_getsig(struct uart_softc *);
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static int adm5120_uart_bus_ioctl(struct uart_softc *, int, intptr_t);
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static int adm5120_uart_bus_ipend(struct uart_softc *);
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static int adm5120_uart_bus_param(struct uart_softc *, int, int, int, int);
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static int adm5120_uart_bus_probe(struct uart_softc *);
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static int adm5120_uart_bus_receive(struct uart_softc *);
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static int adm5120_uart_bus_setsig(struct uart_softc *, int);
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static int adm5120_uart_bus_transmit(struct uart_softc *);
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static void adm5120_uart_bus_grab(struct uart_softc *);
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static void adm5120_uart_bus_ungrab(struct uart_softc *);
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static kobj_method_t adm5120_uart_methods[] = {
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KOBJMETHOD(uart_attach, adm5120_uart_bus_attach),
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KOBJMETHOD(uart_detach, adm5120_uart_bus_detach),
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KOBJMETHOD(uart_flush, adm5120_uart_bus_flush),
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KOBJMETHOD(uart_getsig, adm5120_uart_bus_getsig),
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KOBJMETHOD(uart_ioctl, adm5120_uart_bus_ioctl),
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KOBJMETHOD(uart_ipend, adm5120_uart_bus_ipend),
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KOBJMETHOD(uart_param, adm5120_uart_bus_param),
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KOBJMETHOD(uart_probe, adm5120_uart_bus_probe),
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KOBJMETHOD(uart_receive, adm5120_uart_bus_receive),
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KOBJMETHOD(uart_setsig, adm5120_uart_bus_setsig),
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KOBJMETHOD(uart_transmit, adm5120_uart_bus_transmit),
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KOBJMETHOD(uart_grab, adm5120_uart_bus_grab),
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KOBJMETHOD(uart_ungrab, adm5120_uart_bus_ungrab),
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{ 0, 0 }
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};
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struct uart_class uart_adm5120_uart_class = {
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"adm5120",
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adm5120_uart_methods,
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sizeof(struct adm5120_uart_softc),
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.uc_ops = &uart_adm5120_uart_ops,
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.uc_range = 1, /* use hinted range */
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.uc_rclk = 62500000,
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.uc_rshift = 0
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};
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#define SIGCHG(c, i, s, d) \
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if (c) { \
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i |= (i & s) ? s : s | d; \
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} else { \
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i = (i & s) ? (i & ~s) | d : i; \
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}
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/*
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* Disable TX interrupt. uart should be locked
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*/
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static __inline void
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adm5120_uart_disable_txintr(struct uart_softc *sc)
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{
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uint8_t cr;
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cr = uart_getreg(&sc->sc_bas, UART_CR_REG);
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cr &= ~UART_CR_TX_INT_EN;
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uart_setreg(&sc->sc_bas, UART_CR_REG, cr);
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}
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/*
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* Enable TX interrupt. uart should be locked
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*/
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static __inline void
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adm5120_uart_enable_txintr(struct uart_softc *sc)
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{
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uint8_t cr;
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cr = uart_getreg(&sc->sc_bas, UART_CR_REG);
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cr |= UART_CR_TX_INT_EN;
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uart_setreg(&sc->sc_bas, UART_CR_REG, cr);
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}
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static int
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adm5120_uart_bus_attach(struct uart_softc *sc)
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{
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struct uart_bas *bas;
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struct uart_devinfo *di;
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bas = &sc->sc_bas;
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if (sc->sc_sysdev != NULL) {
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di = sc->sc_sysdev;
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/* TODO: set parameters from di */
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} else {
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/* TODO: set parameters 115200, 8N1 */
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}
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(void)adm5120_uart_bus_getsig(sc);
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#if 1
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/* Enable FIFO */
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uart_setreg(bas, UART_LCR_H_REG,
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uart_getreg(bas, UART_LCR_H_REG) | UART_LCR_H_FEN);
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#endif
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/* Enable interrupts */
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uart_setreg(bas, UART_CR_REG,
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UART_CR_PORT_EN|UART_CR_RX_INT_EN|UART_CR_RX_TIMEOUT_INT_EN|
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UART_CR_MODEM_STATUS_INT_EN);
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return (0);
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}
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static int
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adm5120_uart_bus_detach(struct uart_softc *sc)
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{
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return (0);
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}
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static int
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adm5120_uart_bus_flush(struct uart_softc *sc, int what)
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{
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return (0);
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}
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static int
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adm5120_uart_bus_getsig(struct uart_softc *sc)
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{
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uint32_t new, old, sig;
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uint8_t bes;
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do {
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old = sc->sc_hwsig;
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sig = old;
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uart_lock(sc->sc_hwmtx);
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bes = uart_getreg(&sc->sc_bas, UART_FR_REG);
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uart_unlock(sc->sc_hwmtx);
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SIGCHG(bes & UART_FR_CTS, sig, SER_CTS, SER_DCTS);
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SIGCHG(bes & UART_FR_DCD, sig, SER_DCD, SER_DDCD);
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SIGCHG(bes & UART_FR_DSR, sig, SER_DSR, SER_DDSR);
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new = sig & ~SER_MASK_DELTA;
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} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
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return (sig);
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}
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static int
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adm5120_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
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{
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struct uart_bas *bas;
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int baudrate, divisor, error;
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bas = &sc->sc_bas;
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error = 0;
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uart_lock(sc->sc_hwmtx);
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switch (request) {
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case UART_IOCTL_BREAK:
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/* TODO: Send BREAK */
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break;
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case UART_IOCTL_BAUD:
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divisor = uart_getreg(bas, UART_LCR_M_REG);
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divisor = (divisor << 8) |
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uart_getreg(bas, UART_LCR_L_REG);
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baudrate = bas->rclk / 2 / (divisor + 2);
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*(int*)data = baudrate;
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break;
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default:
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error = EINVAL;
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break;
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}
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uart_unlock(sc->sc_hwmtx);
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return (error);
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}
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static int
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adm5120_uart_bus_ipend(struct uart_softc *sc)
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{
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struct uart_bas *bas;
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int ipend;
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uint8_t ir, fr, rsr;
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bas = &sc->sc_bas;
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ipend = 0;
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uart_lock(sc->sc_hwmtx);
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ir = uart_getreg(&sc->sc_bas, UART_IR_REG);
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fr = uart_getreg(&sc->sc_bas, UART_FR_REG);
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rsr = uart_getreg(&sc->sc_bas, UART_RSR_REG);
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if (ir & UART_IR_RX_INT)
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ipend |= SER_INT_RXREADY;
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if (ir & UART_IR_RX_TIMEOUT_INT)
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ipend |= SER_INT_RXREADY;
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if (ir & UART_IR_MODEM_STATUS_INT)
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ipend |= SER_INT_SIGCHG;
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if (rsr & UART_RSR_BE)
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ipend |= SER_INT_BREAK;
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if (rsr & UART_RSR_OE)
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ipend |= SER_INT_OVERRUN;
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if (fr & UART_FR_TX_FIFO_EMPTY) {
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if (ir & UART_IR_TX_INT) {
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adm5120_uart_disable_txintr(sc);
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ipend |= SER_INT_TXIDLE;
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}
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}
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if (ipend)
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uart_setreg(bas, UART_IR_REG, ir | UART_IR_UICR);
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uart_unlock(sc->sc_hwmtx);
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return (ipend);
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}
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static int
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adm5120_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
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int stopbits, int parity)
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{
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/* TODO: Set parameters for uart, meanwhile stick with 115200 8N1 */
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return (0);
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}
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static int
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adm5120_uart_bus_probe(struct uart_softc *sc)
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{
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char buf[80];
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int error;
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char ch;
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error = adm5120_uart_probe(&sc->sc_bas);
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if (error)
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return (error);
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sc->sc_rxfifosz = 16;
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sc->sc_txfifosz = 16;
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ch = sc->sc_bas.chan + 'A';
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snprintf(buf, sizeof(buf), "adm5120_uart, channel %c", ch);
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device_set_desc_copy(sc->sc_dev, buf);
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return (0);
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}
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static int
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adm5120_uart_bus_receive(struct uart_softc *sc)
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{
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struct uart_bas *bas;
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int xc;
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uint8_t fr, rsr;
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bas = &sc->sc_bas;
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uart_lock(sc->sc_hwmtx);
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fr = uart_getreg(bas, UART_FR_REG);
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while (!(fr & UART_FR_RX_FIFO_EMPTY)) {
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if (uart_rx_full(sc)) {
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sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
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break;
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}
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xc = 0;
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rsr = uart_getreg(bas, UART_RSR_REG);
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if (rsr & UART_RSR_FE)
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xc |= UART_STAT_FRAMERR;
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if (rsr & UART_RSR_PE)
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xc |= UART_STAT_PARERR;
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if (rsr & UART_RSR_OE)
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xc |= UART_STAT_OVERRUN;
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xc |= uart_getreg(bas, UART_DR_REG);
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uart_barrier(bas);
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uart_rx_put(sc, xc);
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if (rsr & (UART_RSR_FE | UART_RSR_PE | UART_RSR_OE)) {
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uart_setreg(bas, UART_ECR_REG, UART_ECR_RSR);
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uart_barrier(bas);
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}
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fr = uart_getreg(bas, UART_FR_REG);
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}
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/* Discard everything left in the Rx FIFO. */
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while (!(fr & UART_FR_RX_FIFO_EMPTY)) {
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( void)uart_getreg(bas, UART_DR_REG);
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uart_barrier(bas);
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rsr = uart_getreg(bas, UART_RSR_REG);
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if (rsr & (UART_RSR_FE | UART_RSR_PE | UART_RSR_OE)) {
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uart_setreg(bas, UART_ECR_REG, UART_ECR_RSR);
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uart_barrier(bas);
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}
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fr = uart_getreg(bas, UART_FR_REG);
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}
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uart_unlock(sc->sc_hwmtx);
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return (0);
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}
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static int
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adm5120_uart_bus_setsig(struct uart_softc *sc, int sig)
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{
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/* TODO: implement (?) */
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return (0);
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}
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static int
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adm5120_uart_bus_transmit(struct uart_softc *sc)
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{
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struct uart_bas *bas;
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bas = &sc->sc_bas;
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uart_lock(sc->sc_hwmtx);
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sc->sc_txbusy = 1;
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for (int i = 0; i < sc->sc_txdatasz; i++) {
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if (uart_getreg(bas, UART_FR_REG) & UART_FR_TX_FIFO_FULL)
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break;
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uart_setreg(bas, UART_DR_REG, sc->sc_txbuf[i]);
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}
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/* Enable TX interrupt */
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adm5120_uart_enable_txintr(sc);
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uart_unlock(sc->sc_hwmtx);
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return (0);
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}
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static void
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adm5120_uart_bus_grab(struct uart_softc *sc)
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{
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/* Enable interrupts - no RX_INT or RX_TIMEOUT */
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uart_lock(sc->sc_hwmtx);
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uart_setreg(&sc->sc_bas, UART_CR_REG,
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UART_CR_PORT_EN | UART_CR_MODEM_STATUS_INT_EN);
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uart_unlock(sc->sc_hwmtx);
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}
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static void
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adm5120_uart_bus_ungrab(struct uart_softc *sc)
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{
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/* Enable interrupts */
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uart_lock(sc->sc_hwmtx);
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uart_setreg(&sc->sc_bas, UART_CR_REG,
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UART_CR_PORT_EN|UART_CR_RX_INT_EN|UART_CR_RX_TIMEOUT_INT_EN|
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UART_CR_MODEM_STATUS_INT_EN);
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uart_unlock(sc->sc_hwmtx);
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}
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