663 lines
17 KiB
C
663 lines
17 KiB
C
/*-
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* Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Allwinner A10/A20 Framebuffer
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/condvar.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/fbio.h>
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#include <vm/vm.h>
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#include <vm/vm_extern.h>
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#include <vm/vm_kern.h>
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#include <vm/pmap.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/videomode/videomode.h>
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#include <dev/videomode/edidvar.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include "fb_if.h"
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#include "hdmi_if.h"
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#define FB_DEFAULT_W 800
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#define FB_DEFAULT_H 600
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#define FB_DEFAULT_REF 60
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#define FB_BPP 32
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#define FB_ALIGN 0x1000
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#define HDMI_ENABLE_DELAY 20000
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#define DEBE_FREQ 300000000
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#define DOT_CLOCK_TO_HZ(c) ((c) * 1000)
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/* Display backend */
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#define DEBE_REG_START 0x800
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#define DEBE_REG_END 0x1000
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#define DEBE_REG_WIDTH 4
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#define DEBE_MODCTL 0x800
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#define MODCTL_ITLMOD_EN (1 << 28)
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#define MODCTL_OUT_SEL_MASK (0x7 << 20)
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#define MODCTL_OUT_SEL(sel) ((sel) << 20)
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#define OUT_SEL_LCD 0
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#define MODCTL_LAY0_EN (1 << 8)
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#define MODCTL_START_CTL (1 << 1)
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#define MODCTL_EN (1 << 0)
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#define DEBE_DISSIZE 0x808
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#define DIS_HEIGHT(h) (((h) - 1) << 16)
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#define DIS_WIDTH(w) (((w) - 1) << 0)
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#define DEBE_LAYSIZE0 0x810
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#define LAY_HEIGHT(h) (((h) - 1) << 16)
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#define LAY_WIDTH(w) (((w) - 1) << 0)
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#define DEBE_LAYCOOR0 0x820
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#define LAY_XCOOR(x) ((x) << 16)
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#define LAY_YCOOR(y) ((y) << 0)
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#define DEBE_LAYLINEWIDTH0 0x840
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#define DEBE_LAYFB_L32ADD0 0x850
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#define LAYFB_L32ADD(pa) ((pa) << 3)
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#define DEBE_LAYFB_H4ADD 0x860
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#define LAY0FB_H4ADD(pa) ((pa) >> 29)
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#define DEBE_REGBUFFCTL 0x870
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#define REGBUFFCTL_LOAD (1 << 0)
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#define DEBE_ATTCTL1 0x8a0
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#define ATTCTL1_FBFMT(fmt) ((fmt) << 8)
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#define FBFMT_XRGB8888 9
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#define ATTCTL1_FBPS(ps) ((ps) << 0)
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#define FBPS_32BPP_ARGB 0
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/* Timing controller */
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#define TCON_GCTL 0x000
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#define GCTL_TCON_EN (1 << 31)
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#define GCTL_IO_MAP_SEL_TCON1 (1 << 0)
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#define TCON_GINT1 0x008
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#define GINT1_TCON1_LINENO(n) (((n) + 2) << 0)
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#define TCON0_DCLK 0x044
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#define DCLK_EN 0xf0000000
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#define TCON1_CTL 0x090
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#define TCON1_EN (1 << 31)
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#define INTERLACE_EN (1 << 20)
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#define TCON1_SRC_SEL(src) ((src) << 0)
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#define TCON1_SRC_CH1 0
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#define TCON1_SRC_CH2 1
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#define TCON1_SRC_BLUE 2
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#define TCON1_START_DELAY(sd) ((sd) << 4)
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#define TCON1_BASIC0 0x094
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#define TCON1_BASIC1 0x098
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#define TCON1_BASIC2 0x09c
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#define TCON1_BASIC3 0x0a0
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#define TCON1_BASIC4 0x0a4
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#define TCON1_BASIC5 0x0a8
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#define BASIC_X(x) (((x) - 1) << 16)
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#define BASIC_Y(y) (((y) - 1) << 0)
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#define BASIC3_HT(ht) (((ht) - 1) << 16)
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#define BASIC3_HBP(hbp) (((hbp) - 1) << 0)
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#define BASIC4_VT(vt) ((vt) << 16)
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#define BASIC4_VBP(vbp) (((vbp) - 1) << 0)
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#define BASIC5_HSPW(hspw) (((hspw) - 1) << 16)
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#define BASIC5_VSPW(vspw) (((vspw) - 1) << 0)
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#define TCON1_IO_POL 0x0f0
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#define IO_POL_IO2_INV (1 << 26)
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#define IO_POL_PHSYNC (1 << 25)
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#define IO_POL_PVSYNC (1 << 24)
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#define TCON1_IO_TRI 0x0f4
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#define IO0_OUTPUT_TRI_EN (1 << 24)
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#define IO1_OUTPUT_TRI_EN (1 << 25)
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#define IO_TRI_MASK 0xffffffff
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#define START_DELAY(vbl) (MIN(32, (vbl)) - 2)
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#define VBLANK_LEN(vt, vd, i) ((((vt) << (i)) >> 1) - (vd) - 2)
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#define VTOTAL(vt) ((vt) * 2)
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#define DIVIDE(x, y) (((x) + ((y) / 2)) / (y))
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struct a10fb_softc {
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device_t dev;
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device_t fbdev;
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struct resource *res[2];
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/* Framebuffer */
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struct fb_info info;
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size_t fbsize;
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bus_addr_t paddr;
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vm_offset_t vaddr;
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/* HDMI */
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eventhandler_tag hdmi_evh;
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};
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static struct resource_spec a10fb_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE }, /* DEBE */
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{ SYS_RES_MEMORY, 1, RF_ACTIVE }, /* TCON */
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{ -1, 0 }
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};
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#define DEBE_READ(sc, reg) bus_read_4((sc)->res[0], (reg))
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#define DEBE_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
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#define TCON_READ(sc, reg) bus_read_4((sc)->res[1], (reg))
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#define TCON_WRITE(sc, reg, val) bus_write_4((sc)->res[1], (reg), (val))
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static int
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a10fb_allocfb(struct a10fb_softc *sc)
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{
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sc->vaddr = kmem_alloc_contig(kernel_arena, sc->fbsize,
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M_NOWAIT | M_ZERO, 0, ~0, FB_ALIGN, 0, VM_MEMATTR_WRITE_COMBINING);
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if (sc->vaddr == 0) {
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device_printf(sc->dev, "failed to allocate FB memory\n");
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return (ENOMEM);
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}
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sc->paddr = pmap_kextract(sc->vaddr);
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return (0);
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}
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static void
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a10fb_freefb(struct a10fb_softc *sc)
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{
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kmem_free(kernel_arena, sc->vaddr, sc->fbsize);
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}
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static int
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a10fb_setup_debe(struct a10fb_softc *sc, const struct videomode *mode)
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{
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int width, height, interlace, reg;
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clk_t clk_ahb, clk_dram, clk_debe;
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hwreset_t rst;
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uint32_t val;
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int error;
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interlace = !!(mode->flags & VID_INTERLACE);
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width = mode->hdisplay;
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height = mode->vdisplay << interlace;
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/* Leave reset */
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error = hwreset_get_by_ofw_name(sc->dev, "de_be", &rst);
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if (error != 0) {
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device_printf(sc->dev, "cannot find reset 'de_be'\n");
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return (error);
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}
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error = hwreset_deassert(rst);
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if (error != 0) {
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device_printf(sc->dev, "couldn't de-assert reset 'de_be'\n");
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return (error);
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}
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/* Gating AHB clock for BE */
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error = clk_get_by_ofw_name(sc->dev, "ahb_de_be", &clk_ahb);
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if (error != 0) {
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device_printf(sc->dev, "cannot find clk 'ahb_de_be'\n");
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return (error);
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}
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error = clk_enable(clk_ahb);
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if (error != 0) {
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device_printf(sc->dev, "cannot enable clk 'ahb_de_be'\n");
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return (error);
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}
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/* Enable DRAM clock to BE */
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error = clk_get_by_ofw_name(sc->dev, "dram_de_be", &clk_dram);
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if (error != 0) {
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device_printf(sc->dev, "cannot find clk 'dram_de_be'\n");
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return (error);
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}
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error = clk_enable(clk_dram);
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if (error != 0) {
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device_printf(sc->dev, "cannot enable clk 'dram_de_be'\n");
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return (error);
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}
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/* Set BE clock to 300MHz and enable */
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error = clk_get_by_ofw_name(sc->dev, "de_be", &clk_debe);
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if (error != 0) {
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device_printf(sc->dev, "cannot find clk 'de_be'\n");
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return (error);
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}
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error = clk_set_freq(clk_debe, DEBE_FREQ, CLK_SET_ROUND_DOWN);
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if (error != 0) {
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device_printf(sc->dev, "cannot set 'de_be' frequency\n");
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return (error);
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}
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error = clk_enable(clk_debe);
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if (error != 0) {
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device_printf(sc->dev, "cannot enable clk 'de_be'\n");
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return (error);
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}
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/* Initialize all registers to 0 */
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for (reg = DEBE_REG_START; reg < DEBE_REG_END; reg += DEBE_REG_WIDTH)
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DEBE_WRITE(sc, reg, 0);
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/* Enable display backend */
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DEBE_WRITE(sc, DEBE_MODCTL, MODCTL_EN);
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/* Set display size */
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DEBE_WRITE(sc, DEBE_DISSIZE, DIS_HEIGHT(height) | DIS_WIDTH(width));
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/* Set layer 0 size, position, and stride */
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DEBE_WRITE(sc, DEBE_LAYSIZE0, LAY_HEIGHT(height) | LAY_WIDTH(width));
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DEBE_WRITE(sc, DEBE_LAYCOOR0, LAY_XCOOR(0) | LAY_YCOOR(0));
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DEBE_WRITE(sc, DEBE_LAYLINEWIDTH0, width * FB_BPP);
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/* Point layer 0 to FB memory */
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DEBE_WRITE(sc, DEBE_LAYFB_L32ADD0, LAYFB_L32ADD(sc->paddr));
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DEBE_WRITE(sc, DEBE_LAYFB_H4ADD, LAY0FB_H4ADD(sc->paddr));
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/* Set backend format and pixel sequence */
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DEBE_WRITE(sc, DEBE_ATTCTL1, ATTCTL1_FBFMT(FBFMT_XRGB8888) |
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ATTCTL1_FBPS(FBPS_32BPP_ARGB));
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/* Enable layer 0, output to LCD, setup interlace */
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val = DEBE_READ(sc, DEBE_MODCTL);
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val |= MODCTL_LAY0_EN;
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val &= ~MODCTL_OUT_SEL_MASK;
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val |= MODCTL_OUT_SEL(OUT_SEL_LCD);
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if (interlace)
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val |= MODCTL_ITLMOD_EN;
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else
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val &= ~MODCTL_ITLMOD_EN;
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DEBE_WRITE(sc, DEBE_MODCTL, val);
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/* Commit settings */
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DEBE_WRITE(sc, DEBE_REGBUFFCTL, REGBUFFCTL_LOAD);
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/* Start DEBE */
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val = DEBE_READ(sc, DEBE_MODCTL);
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val |= MODCTL_START_CTL;
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DEBE_WRITE(sc, DEBE_MODCTL, val);
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return (0);
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}
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static int
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a10fb_setup_pll(struct a10fb_softc *sc, uint64_t freq)
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{
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clk_t clk_sclk1, clk_sclk2;
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int error;
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error = clk_get_by_ofw_name(sc->dev, "lcd_ch1_sclk1", &clk_sclk1);
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if (error != 0) {
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device_printf(sc->dev, "cannot find clk 'lcd_ch1_sclk1'\n");
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return (error);
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}
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error = clk_get_by_ofw_name(sc->dev, "lcd_ch1_sclk2", &clk_sclk2);
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if (error != 0) {
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device_printf(sc->dev, "cannot find clk 'lcd_ch1_sclk2'\n");
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return (error);
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}
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error = clk_set_freq(clk_sclk2, freq, 0);
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if (error != 0) {
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device_printf(sc->dev, "cannot set lcd ch1 frequency\n");
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return (error);
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}
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error = clk_enable(clk_sclk2);
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if (error != 0) {
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device_printf(sc->dev, "cannot enable lcd ch1 sclk2\n");
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return (error);
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}
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error = clk_enable(clk_sclk1);
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if (error != 0) {
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device_printf(sc->dev, "cannot enable lcd ch1 sclk1\n");
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return (error);
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}
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return (0);
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}
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static int
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a10fb_setup_tcon(struct a10fb_softc *sc, const struct videomode *mode)
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{
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u_int interlace, hspw, hbp, vspw, vbp, vbl, width, height, start_delay;
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u_int vtotal, framerate, clk;
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clk_t clk_ahb;
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hwreset_t rst;
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uint32_t val;
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int error;
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interlace = !!(mode->flags & VID_INTERLACE);
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width = mode->hdisplay;
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height = mode->vdisplay;
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hspw = mode->hsync_end - mode->hsync_start;
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hbp = mode->htotal - mode->hsync_start;
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vspw = mode->vsync_end - mode->vsync_start;
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vbp = mode->vtotal - mode->vsync_start;
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vbl = VBLANK_LEN(mode->vtotal, mode->vdisplay, interlace);
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start_delay = START_DELAY(vbl);
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/* Leave reset */
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error = hwreset_get_by_ofw_name(sc->dev, "lcd", &rst);
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if (error != 0) {
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device_printf(sc->dev, "cannot find reset 'lcd'\n");
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return (error);
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}
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error = hwreset_deassert(rst);
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if (error != 0) {
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device_printf(sc->dev, "couldn't de-assert reset 'lcd'\n");
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return (error);
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}
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/* Gating AHB clock for LCD */
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error = clk_get_by_ofw_name(sc->dev, "ahb_lcd", &clk_ahb);
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if (error != 0) {
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device_printf(sc->dev, "cannot find clk 'ahb_lcd'\n");
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return (error);
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}
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error = clk_enable(clk_ahb);
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if (error != 0) {
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device_printf(sc->dev, "cannot enable clk 'ahb_lcd'\n");
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return (error);
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}
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/* Disable TCON and TCON1 */
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TCON_WRITE(sc, TCON_GCTL, 0);
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TCON_WRITE(sc, TCON1_CTL, 0);
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/* Enable clocks */
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TCON_WRITE(sc, TCON0_DCLK, DCLK_EN);
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/* Disable IO and data output ports */
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TCON_WRITE(sc, TCON1_IO_TRI, IO_TRI_MASK);
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/* Disable TCON and select TCON1 */
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TCON_WRITE(sc, TCON_GCTL, GCTL_IO_MAP_SEL_TCON1);
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/* Source width and height */
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TCON_WRITE(sc, TCON1_BASIC0, BASIC_X(width) | BASIC_Y(height));
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/* Scaler width and height */
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TCON_WRITE(sc, TCON1_BASIC1, BASIC_X(width) | BASIC_Y(height));
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/* Output width and height */
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TCON_WRITE(sc, TCON1_BASIC2, BASIC_X(width) | BASIC_Y(height));
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/* Horizontal total and back porch */
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TCON_WRITE(sc, TCON1_BASIC3, BASIC3_HT(mode->htotal) | BASIC3_HBP(hbp));
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/* Vertical total and back porch */
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vtotal = VTOTAL(mode->vtotal);
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if (interlace) {
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framerate = DIVIDE(DIVIDE(DOT_CLOCK_TO_HZ(mode->dot_clock),
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mode->htotal), mode->vtotal);
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clk = mode->htotal * (VTOTAL(mode->vtotal) + 1) * framerate;
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if ((clk / 2) == DOT_CLOCK_TO_HZ(mode->dot_clock))
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vtotal += 1;
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}
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TCON_WRITE(sc, TCON1_BASIC4, BASIC4_VT(vtotal) | BASIC4_VBP(vbp));
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/* Horizontal and vertical sync */
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TCON_WRITE(sc, TCON1_BASIC5, BASIC5_HSPW(hspw) | BASIC5_VSPW(vspw));
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/* Polarity */
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val = IO_POL_IO2_INV;
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if (mode->flags & VID_PHSYNC)
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val |= IO_POL_PHSYNC;
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if (mode->flags & VID_PVSYNC)
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val |= IO_POL_PVSYNC;
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TCON_WRITE(sc, TCON1_IO_POL, val);
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/* Set scan line for TCON1 line trigger */
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TCON_WRITE(sc, TCON_GINT1, GINT1_TCON1_LINENO(start_delay));
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/* Enable TCON1 */
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val = TCON1_EN;
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if (interlace)
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val |= INTERLACE_EN;
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val |= TCON1_START_DELAY(start_delay);
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val |= TCON1_SRC_SEL(TCON1_SRC_CH1);
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TCON_WRITE(sc, TCON1_CTL, val);
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/* Setup PLL */
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return (a10fb_setup_pll(sc, DOT_CLOCK_TO_HZ(mode->dot_clock)));
|
|
}
|
|
|
|
static void
|
|
a10fb_enable_tcon(struct a10fb_softc *sc, int onoff)
|
|
{
|
|
uint32_t val;
|
|
|
|
/* Enable TCON */
|
|
val = TCON_READ(sc, TCON_GCTL);
|
|
if (onoff)
|
|
val |= GCTL_TCON_EN;
|
|
else
|
|
val &= ~GCTL_TCON_EN;
|
|
TCON_WRITE(sc, TCON_GCTL, val);
|
|
|
|
/* Enable TCON1 IO0/IO1 outputs */
|
|
val = TCON_READ(sc, TCON1_IO_TRI);
|
|
if (onoff)
|
|
val &= ~(IO0_OUTPUT_TRI_EN | IO1_OUTPUT_TRI_EN);
|
|
else
|
|
val |= (IO0_OUTPUT_TRI_EN | IO1_OUTPUT_TRI_EN);
|
|
TCON_WRITE(sc, TCON1_IO_TRI, val);
|
|
}
|
|
|
|
static int
|
|
a10fb_configure(struct a10fb_softc *sc, const struct videomode *mode)
|
|
{
|
|
size_t fbsize;
|
|
int error;
|
|
|
|
fbsize = round_page(mode->hdisplay * mode->vdisplay * (FB_BPP / NBBY));
|
|
|
|
/* Detach the old FB device */
|
|
if (sc->fbdev != NULL) {
|
|
device_delete_child(sc->dev, sc->fbdev);
|
|
sc->fbdev = NULL;
|
|
}
|
|
|
|
/* If the FB size has changed, free the old FB memory */
|
|
if (sc->fbsize > 0 && sc->fbsize != fbsize) {
|
|
a10fb_freefb(sc);
|
|
sc->vaddr = 0;
|
|
}
|
|
|
|
/* Allocate the FB if necessary */
|
|
sc->fbsize = fbsize;
|
|
if (sc->vaddr == 0) {
|
|
error = a10fb_allocfb(sc);
|
|
if (error != 0) {
|
|
device_printf(sc->dev, "failed to allocate FB memory\n");
|
|
return (ENXIO);
|
|
}
|
|
}
|
|
|
|
/* Setup display backend */
|
|
error = a10fb_setup_debe(sc, mode);
|
|
if (error != 0)
|
|
return (error);
|
|
|
|
/* Setup display timing controller */
|
|
error = a10fb_setup_tcon(sc, mode);
|
|
if (error != 0)
|
|
return (error);
|
|
|
|
/* Attach framebuffer device */
|
|
sc->info.fb_name = device_get_nameunit(sc->dev);
|
|
sc->info.fb_vbase = (intptr_t)sc->vaddr;
|
|
sc->info.fb_pbase = sc->paddr;
|
|
sc->info.fb_size = sc->fbsize;
|
|
sc->info.fb_bpp = sc->info.fb_depth = FB_BPP;
|
|
sc->info.fb_stride = mode->hdisplay * (FB_BPP / NBBY);
|
|
sc->info.fb_width = mode->hdisplay;
|
|
sc->info.fb_height = mode->vdisplay;
|
|
|
|
sc->fbdev = device_add_child(sc->dev, "fbd", device_get_unit(sc->dev));
|
|
if (sc->fbdev == NULL) {
|
|
device_printf(sc->dev, "failed to add fbd child\n");
|
|
return (ENOENT);
|
|
}
|
|
|
|
error = device_probe_and_attach(sc->fbdev);
|
|
if (error != 0) {
|
|
device_printf(sc->dev, "failed to attach fbd device\n");
|
|
return (error);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
a10fb_hdmi_event(void *arg, device_t hdmi_dev)
|
|
{
|
|
const struct videomode *mode;
|
|
struct videomode hdmi_mode;
|
|
struct a10fb_softc *sc;
|
|
struct edid_info ei;
|
|
uint8_t *edid;
|
|
uint32_t edid_len;
|
|
int error;
|
|
|
|
sc = arg;
|
|
edid = NULL;
|
|
edid_len = 0;
|
|
mode = NULL;
|
|
|
|
error = HDMI_GET_EDID(hdmi_dev, &edid, &edid_len);
|
|
if (error != 0) {
|
|
device_printf(sc->dev, "failed to get EDID: %d\n", error);
|
|
} else {
|
|
error = edid_parse(edid, &ei);
|
|
if (error != 0) {
|
|
device_printf(sc->dev, "failed to parse EDID: %d\n",
|
|
error);
|
|
} else {
|
|
if (bootverbose)
|
|
edid_print(&ei);
|
|
mode = ei.edid_preferred_mode;
|
|
}
|
|
}
|
|
|
|
/* If the preferred mode could not be determined, use the default */
|
|
if (mode == NULL)
|
|
mode = pick_mode_by_ref(FB_DEFAULT_W, FB_DEFAULT_H,
|
|
FB_DEFAULT_REF);
|
|
|
|
if (mode == NULL) {
|
|
device_printf(sc->dev, "failed to find usable video mode\n");
|
|
return;
|
|
}
|
|
|
|
if (bootverbose)
|
|
device_printf(sc->dev, "using %dx%d\n",
|
|
mode->hdisplay, mode->vdisplay);
|
|
|
|
/* Disable HDMI */
|
|
HDMI_ENABLE(hdmi_dev, 0);
|
|
|
|
/* Disable timing controller */
|
|
a10fb_enable_tcon(sc, 0);
|
|
|
|
/* Configure DEBE and TCON */
|
|
error = a10fb_configure(sc, mode);
|
|
if (error != 0) {
|
|
device_printf(sc->dev, "failed to configure FB: %d\n", error);
|
|
return;
|
|
}
|
|
|
|
hdmi_mode = *mode;
|
|
hdmi_mode.hskew = mode->hsync_end - mode->hsync_start;
|
|
hdmi_mode.flags |= VID_HSKEW;
|
|
HDMI_SET_VIDEOMODE(hdmi_dev, &hdmi_mode);
|
|
|
|
/* Enable timing controller */
|
|
a10fb_enable_tcon(sc, 1);
|
|
|
|
DELAY(HDMI_ENABLE_DELAY);
|
|
|
|
/* Enable HDMI */
|
|
HDMI_ENABLE(hdmi_dev, 1);
|
|
}
|
|
|
|
static int
|
|
a10fb_probe(device_t dev)
|
|
{
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
|
|
if (!ofw_bus_is_compatible(dev, "allwinner,sun7i-a20-fb"))
|
|
return (ENXIO);
|
|
|
|
device_set_desc(dev, "Allwinner Framebuffer");
|
|
return (BUS_PROBE_DEFAULT);
|
|
}
|
|
|
|
static int
|
|
a10fb_attach(device_t dev)
|
|
{
|
|
struct a10fb_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
sc->dev = dev;
|
|
|
|
if (bus_alloc_resources(dev, a10fb_spec, sc->res)) {
|
|
device_printf(dev, "cannot allocate resources for device\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
sc->hdmi_evh = EVENTHANDLER_REGISTER(hdmi_event,
|
|
a10fb_hdmi_event, sc, 0);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static struct fb_info *
|
|
a10fb_fb_getinfo(device_t dev)
|
|
{
|
|
struct a10fb_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
return (&sc->info);
|
|
}
|
|
|
|
static device_method_t a10fb_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, a10fb_probe),
|
|
DEVMETHOD(device_attach, a10fb_attach),
|
|
|
|
/* FB interface */
|
|
DEVMETHOD(fb_getinfo, a10fb_fb_getinfo),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t a10fb_driver = {
|
|
"fb",
|
|
a10fb_methods,
|
|
sizeof(struct a10fb_softc),
|
|
};
|
|
|
|
static devclass_t a10fb_devclass;
|
|
|
|
DRIVER_MODULE(fb, simplebus, a10fb_driver, a10fb_devclass, 0, 0);
|