712 lines
17 KiB
C
712 lines
17 KiB
C
/*-
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* Copyright (c) 2013 Ganbold Tsagaankhuu <ganbold@freebsd.org>
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* Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
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* Copyright (c) 2012 Luiz Otavio O Souza.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/gpio.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/resource.h>
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#include <machine/intr.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/fdt/fdt_pinctrl.h>
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#include <dev/gpio/gpiobusvar.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/allwinner/allwinner_machdep.h>
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#include <arm/allwinner/allwinner_pinctrl.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include "gpio_if.h"
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#define A10_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \
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GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN)
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#define A10_GPIO_NONE 0
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#define A10_GPIO_PULLUP 1
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#define A10_GPIO_PULLDOWN 2
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#define A10_GPIO_INPUT 0
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#define A10_GPIO_OUTPUT 1
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#define AW_GPIO_DRV_MASK 0x3
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#define AW_GPIO_PUD_MASK 0x3
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#define AW_PINCTRL 1
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#define AW_R_PINCTRL 2
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/* Defined in a10_padconf.c */
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#ifdef SOC_ALLWINNER_A10
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extern const struct allwinner_padconf a10_padconf;
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#endif
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/* Defined in a20_padconf.c */
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#ifdef SOC_ALLWINNER_A20
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extern const struct allwinner_padconf a20_padconf;
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#endif
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/* Defined in a31_padconf.c */
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#ifdef SOC_ALLWINNER_A31
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extern const struct allwinner_padconf a31_padconf;
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#endif
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/* Defined in a31s_padconf.c */
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#ifdef SOC_ALLWINNER_A31S
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extern const struct allwinner_padconf a31s_padconf;
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#endif
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#if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S)
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extern const struct allwinner_padconf a31_r_padconf;
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#endif
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/* Defined in h3_padconf.c */
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#ifdef SOC_ALLWINNER_H3
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extern const struct allwinner_padconf h3_padconf;
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extern const struct allwinner_padconf h3_r_padconf;
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#endif
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/* Defined in a83t_padconf.c */
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#ifdef SOC_ALLWINNER_A83T
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extern const struct allwinner_padconf a83t_padconf;
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extern const struct allwinner_padconf a83t_r_padconf;
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#endif
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static struct ofw_compat_data compat_data[] = {
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#ifdef SOC_ALLWINNER_A10
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{"allwinner,sun4i-a10-pinctrl", (uintptr_t)&a10_padconf},
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#endif
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#ifdef SOC_ALLWINNER_A20
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{"allwinner,sun7i-a20-pinctrl", (uintptr_t)&a20_padconf},
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#endif
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#ifdef SOC_ALLWINNER_A31
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{"allwinner,sun6i-a31-pinctrl", (uintptr_t)&a31_padconf},
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#endif
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#ifdef SOC_ALLWINNER_A31S
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{"allwinner,sun6i-a31s-pinctrl", (uintptr_t)&a31s_padconf},
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#endif
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#if defined(SOC_ALLWINNER_A31) || defined(SOC_ALLWINNER_A31S)
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{"allwinner,sun6i-a31-r-pinctrl", (uintptr_t)&a31_r_padconf},
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#endif
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#ifdef SOC_ALLWINNER_A83T
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{"allwinner,sun8i-a83t-pinctrl", (uintptr_t)&a83t_padconf},
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{"allwinner,sun8i-a83t-r-pinctrl", (uintptr_t)&a83t_r_padconf},
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#endif
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#ifdef SOC_ALLWINNER_H3
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{"allwinner,sun8i-h3-pinctrl", (uintptr_t)&h3_padconf},
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{"allwinner,sun8i-h3-r-pinctrl", (uintptr_t)&h3_r_padconf},
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#endif
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{NULL, 0}
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};
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struct a10_gpio_softc {
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device_t sc_dev;
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device_t sc_busdev;
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struct mtx sc_mtx;
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struct resource * sc_mem_res;
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struct resource * sc_irq_res;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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void * sc_intrhand;
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const struct allwinner_padconf * padconf;
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};
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#define A10_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
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#define A10_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
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#define A10_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
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#define A10_GPIO_GP_CFG(_bank, _idx) 0x00 + ((_bank) * 0x24) + ((_idx) << 2)
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#define A10_GPIO_GP_DAT(_bank) 0x10 + ((_bank) * 0x24)
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#define A10_GPIO_GP_DRV(_bank, _idx) 0x14 + ((_bank) * 0x24) + ((_idx) << 2)
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#define A10_GPIO_GP_PUL(_bank, _idx) 0x1c + ((_bank) * 0x24) + ((_idx) << 2)
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#define A10_GPIO_GP_INT_CFG0 0x200
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#define A10_GPIO_GP_INT_CFG1 0x204
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#define A10_GPIO_GP_INT_CFG2 0x208
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#define A10_GPIO_GP_INT_CFG3 0x20c
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#define A10_GPIO_GP_INT_CTL 0x210
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#define A10_GPIO_GP_INT_STA 0x214
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#define A10_GPIO_GP_INT_DEB 0x218
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#define A10_GPIO_WRITE(_sc, _off, _val) \
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bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val)
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#define A10_GPIO_READ(_sc, _off) \
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bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off)
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static uint32_t
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a10_gpio_get_function(struct a10_gpio_softc *sc, uint32_t pin)
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{
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uint32_t bank, func, offset;
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/* Must be called with lock held. */
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A10_GPIO_LOCK_ASSERT(sc);
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if (pin > sc->padconf->npins)
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return (0);
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bank = sc->padconf->pins[pin].port;
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pin = sc->padconf->pins[pin].pin;
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offset = ((pin & 0x07) << 2);
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func = A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, pin >> 3));
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switch ((func >> offset) & 0x7) {
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case A10_GPIO_INPUT:
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return (GPIO_PIN_INPUT);
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case A10_GPIO_OUTPUT:
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return (GPIO_PIN_OUTPUT);
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}
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return (0);
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}
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static void
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a10_gpio_set_function(struct a10_gpio_softc *sc, uint32_t pin, uint32_t f)
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{
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uint32_t bank, data, offset;
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/* Must be called with lock held. */
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A10_GPIO_LOCK_ASSERT(sc);
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bank = sc->padconf->pins[pin].port;
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pin = sc->padconf->pins[pin].pin;
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offset = ((pin & 0x07) << 2);
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data = A10_GPIO_READ(sc, A10_GPIO_GP_CFG(bank, pin >> 3));
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data &= ~(7 << offset);
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data |= (f << offset);
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A10_GPIO_WRITE(sc, A10_GPIO_GP_CFG(bank, pin >> 3), data);
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}
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static uint32_t
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a10_gpio_get_pud(struct a10_gpio_softc *sc, uint32_t pin)
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{
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uint32_t bank, offset, val;
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/* Must be called with lock held. */
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A10_GPIO_LOCK_ASSERT(sc);
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bank = sc->padconf->pins[pin].port;
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pin = sc->padconf->pins[pin].pin;
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offset = ((pin & 0x0f) << 1);
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val = A10_GPIO_READ(sc, A10_GPIO_GP_PUL(bank, pin >> 4));
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switch ((val >> offset) & 0x3) {
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case A10_GPIO_PULLDOWN:
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return (GPIO_PIN_PULLDOWN);
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case A10_GPIO_PULLUP:
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return (GPIO_PIN_PULLUP);
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}
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return (0);
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}
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static void
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a10_gpio_set_pud(struct a10_gpio_softc *sc, uint32_t pin, uint32_t state)
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{
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uint32_t bank, offset, val;
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/* Must be called with lock held. */
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A10_GPIO_LOCK_ASSERT(sc);
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bank = sc->padconf->pins[pin].port;
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pin = sc->padconf->pins[pin].pin;
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offset = ((pin & 0x0f) << 1);
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val = A10_GPIO_READ(sc, A10_GPIO_GP_PUL(bank, pin >> 4));
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val &= ~(AW_GPIO_PUD_MASK << offset);
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val |= (state << offset);
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A10_GPIO_WRITE(sc, A10_GPIO_GP_PUL(bank, pin >> 4), val);
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}
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static void
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a10_gpio_set_drv(struct a10_gpio_softc *sc, uint32_t pin, uint32_t drive)
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{
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uint32_t bank, offset, val;
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/* Must be called with lock held. */
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A10_GPIO_LOCK_ASSERT(sc);
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bank = sc->padconf->pins[pin].port;
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pin = sc->padconf->pins[pin].pin;
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offset = ((pin & 0x0f) << 1);
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val = A10_GPIO_READ(sc, A10_GPIO_GP_DRV(bank, pin >> 4));
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val &= ~(AW_GPIO_DRV_MASK << offset);
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val |= (drive << offset);
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A10_GPIO_WRITE(sc, A10_GPIO_GP_DRV(bank, pin >> 4), val);
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}
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static void
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a10_gpio_pin_configure(struct a10_gpio_softc *sc, uint32_t pin, uint32_t flags)
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{
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/* Must be called with lock held. */
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A10_GPIO_LOCK_ASSERT(sc);
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/* Manage input/output. */
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if (flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) {
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if (flags & GPIO_PIN_OUTPUT)
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a10_gpio_set_function(sc, pin, A10_GPIO_OUTPUT);
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else
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a10_gpio_set_function(sc, pin, A10_GPIO_INPUT);
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}
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/* Manage Pull-up/pull-down. */
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if (flags & (GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN)) {
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if (flags & GPIO_PIN_PULLUP)
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a10_gpio_set_pud(sc, pin, A10_GPIO_PULLUP);
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else
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a10_gpio_set_pud(sc, pin, A10_GPIO_PULLDOWN);
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} else
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a10_gpio_set_pud(sc, pin, A10_GPIO_NONE);
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}
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static device_t
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a10_gpio_get_bus(device_t dev)
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{
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struct a10_gpio_softc *sc;
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sc = device_get_softc(dev);
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return (sc->sc_busdev);
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}
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static int
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a10_gpio_pin_max(device_t dev, int *maxpin)
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{
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struct a10_gpio_softc *sc;
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sc = device_get_softc(dev);
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*maxpin = sc->padconf->npins - 1;
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return (0);
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}
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static int
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a10_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
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{
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struct a10_gpio_softc *sc;
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sc = device_get_softc(dev);
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if (pin >= sc->padconf->npins)
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return (EINVAL);
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*caps = A10_GPIO_DEFAULT_CAPS;
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return (0);
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}
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static int
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a10_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
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{
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struct a10_gpio_softc *sc;
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sc = device_get_softc(dev);
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if (pin >= sc->padconf->npins)
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return (EINVAL);
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A10_GPIO_LOCK(sc);
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*flags = a10_gpio_get_function(sc, pin);
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*flags |= a10_gpio_get_pud(sc, pin);
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A10_GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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a10_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
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{
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struct a10_gpio_softc *sc;
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sc = device_get_softc(dev);
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if (pin >= sc->padconf->npins)
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return (EINVAL);
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snprintf(name, GPIOMAXNAME - 1, "%s",
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sc->padconf->pins[pin].name);
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name[GPIOMAXNAME - 1] = '\0';
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return (0);
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}
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static int
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a10_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
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{
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struct a10_gpio_softc *sc;
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sc = device_get_softc(dev);
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if (pin > sc->padconf->npins)
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return (EINVAL);
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A10_GPIO_LOCK(sc);
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a10_gpio_pin_configure(sc, pin, flags);
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A10_GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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a10_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
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{
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struct a10_gpio_softc *sc;
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uint32_t bank, data;
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sc = device_get_softc(dev);
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if (pin > sc->padconf->npins)
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return (EINVAL);
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bank = sc->padconf->pins[pin].port;
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pin = sc->padconf->pins[pin].pin;
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A10_GPIO_LOCK(sc);
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data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
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if (value)
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data |= (1 << pin);
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else
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data &= ~(1 << pin);
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A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data);
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A10_GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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a10_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
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{
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struct a10_gpio_softc *sc;
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uint32_t bank, reg_data;
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sc = device_get_softc(dev);
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if (pin > sc->padconf->npins)
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return (EINVAL);
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bank = sc->padconf->pins[pin].port;
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pin = sc->padconf->pins[pin].pin;
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A10_GPIO_LOCK(sc);
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reg_data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
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A10_GPIO_UNLOCK(sc);
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*val = (reg_data & (1 << pin)) ? 1 : 0;
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return (0);
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}
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static int
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a10_gpio_pin_toggle(device_t dev, uint32_t pin)
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{
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struct a10_gpio_softc *sc;
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uint32_t bank, data;
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sc = device_get_softc(dev);
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if (pin > sc->padconf->npins)
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return (EINVAL);
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bank = sc->padconf->pins[pin].port;
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pin = sc->padconf->pins[pin].pin;
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A10_GPIO_LOCK(sc);
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data = A10_GPIO_READ(sc, A10_GPIO_GP_DAT(bank));
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if (data & (1 << pin))
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data &= ~(1 << pin);
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else
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data |= (1 << pin);
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A10_GPIO_WRITE(sc, A10_GPIO_GP_DAT(bank), data);
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A10_GPIO_UNLOCK(sc);
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return (0);
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}
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static int
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aw_find_pinnum_by_name(struct a10_gpio_softc *sc, const char *pinname)
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{
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int i;
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for (i = 0; i < sc->padconf->npins; i++)
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if (!strcmp(pinname, sc->padconf->pins[i].name))
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return i;
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return (-1);
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}
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static int
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aw_find_pin_func(struct a10_gpio_softc *sc, int pin, const char *func)
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{
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int i;
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for (i = 0; i < AW_MAX_FUNC_BY_PIN; i++)
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if (sc->padconf->pins[pin].functions[i] &&
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!strcmp(func, sc->padconf->pins[pin].functions[i]))
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return (i);
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return (-1);
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}
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static int
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aw_fdt_configure_pins(device_t dev, phandle_t cfgxref)
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{
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struct a10_gpio_softc *sc;
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phandle_t node;
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const char **pinlist = NULL;
|
|
char *pin_function = NULL;
|
|
uint32_t pin_drive, pin_pull;
|
|
int pins_nb, pin_num, pin_func, i, ret;
|
|
|
|
sc = device_get_softc(dev);
|
|
node = OF_node_from_xref(cfgxref);
|
|
ret = 0;
|
|
|
|
/* Getting all prop for configuring pins */
|
|
pins_nb = ofw_bus_string_list_to_array(node, "allwinner,pins", &pinlist);
|
|
if (pins_nb <= 0)
|
|
return (ENOENT);
|
|
if (OF_getprop_alloc(node, "allwinner,function",
|
|
sizeof(*pin_function),
|
|
(void **)&pin_function) == -1) {
|
|
ret = ENOENT;
|
|
goto out;
|
|
}
|
|
if (OF_getencprop(node, "allwinner,drive",
|
|
&pin_drive, sizeof(pin_drive)) == -1) {
|
|
ret = ENOENT;
|
|
goto out;
|
|
}
|
|
if (OF_getencprop(node, "allwinner,pull",
|
|
&pin_pull, sizeof(pin_pull)) == -1) {
|
|
ret = ENOENT;
|
|
goto out;
|
|
}
|
|
|
|
/* Configure each pin to the correct function, drive and pull */
|
|
for (i = 0; i < pins_nb; i++) {
|
|
pin_num = aw_find_pinnum_by_name(sc, pinlist[i]);
|
|
if (pin_num == -1) {
|
|
ret = ENOENT;
|
|
goto out;
|
|
}
|
|
pin_func = aw_find_pin_func(sc, pin_num, pin_function);
|
|
if (pin_func == -1) {
|
|
ret = ENOENT;
|
|
goto out;
|
|
}
|
|
|
|
A10_GPIO_LOCK(sc);
|
|
a10_gpio_set_function(sc, pin_num, pin_func);
|
|
a10_gpio_set_drv(sc, pin_num, pin_drive);
|
|
a10_gpio_set_pud(sc, pin_num, pin_pull);
|
|
A10_GPIO_UNLOCK(sc);
|
|
}
|
|
|
|
out:
|
|
OF_prop_free(pinlist);
|
|
OF_prop_free(pin_function);
|
|
return (ret);
|
|
}
|
|
|
|
static int
|
|
a10_gpio_probe(device_t dev)
|
|
{
|
|
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
|
|
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
|
|
return (ENXIO);
|
|
|
|
device_set_desc(dev, "Allwinner GPIO/Pinmux controller");
|
|
return (BUS_PROBE_DEFAULT);
|
|
}
|
|
|
|
static int
|
|
a10_gpio_attach(device_t dev)
|
|
{
|
|
int rid, error;
|
|
phandle_t gpio;
|
|
struct a10_gpio_softc *sc;
|
|
clk_t clk;
|
|
hwreset_t rst;
|
|
|
|
sc = device_get_softc(dev);
|
|
sc->sc_dev = dev;
|
|
|
|
mtx_init(&sc->sc_mtx, "a10 gpio", "gpio", MTX_SPIN);
|
|
|
|
rid = 0;
|
|
sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
|
|
RF_ACTIVE);
|
|
if (!sc->sc_mem_res) {
|
|
device_printf(dev, "cannot allocate memory window\n");
|
|
goto fail;
|
|
}
|
|
|
|
sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
|
|
sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
|
|
|
|
rid = 0;
|
|
sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
|
|
RF_ACTIVE);
|
|
if (!sc->sc_irq_res) {
|
|
device_printf(dev, "cannot allocate interrupt\n");
|
|
goto fail;
|
|
}
|
|
|
|
/* Find our node. */
|
|
gpio = ofw_bus_get_node(sc->sc_dev);
|
|
if (!OF_hasprop(gpio, "gpio-controller"))
|
|
/* Node is not a GPIO controller. */
|
|
goto fail;
|
|
|
|
/* Use the right pin data for the current SoC */
|
|
sc->padconf = (struct allwinner_padconf *)ofw_bus_search_compatible(dev,
|
|
compat_data)->ocd_data;
|
|
|
|
if (hwreset_get_by_ofw_idx(dev, 0, &rst) == 0) {
|
|
error = hwreset_deassert(rst);
|
|
if (error != 0) {
|
|
device_printf(dev, "cannot de-assert reset\n");
|
|
return (error);
|
|
}
|
|
}
|
|
|
|
if (clk_get_by_ofw_index(dev, 0, &clk) == 0) {
|
|
error = clk_enable(clk);
|
|
if (error != 0) {
|
|
device_printf(dev, "could not enable clock\n");
|
|
return (error);
|
|
}
|
|
}
|
|
|
|
sc->sc_busdev = gpiobus_attach_bus(dev);
|
|
if (sc->sc_busdev == NULL)
|
|
goto fail;
|
|
|
|
/*
|
|
* Register as a pinctrl device
|
|
*/
|
|
fdt_pinctrl_register(dev, "allwinner,pins");
|
|
fdt_pinctrl_configure_tree(dev);
|
|
|
|
return (0);
|
|
|
|
fail:
|
|
if (sc->sc_irq_res)
|
|
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
|
|
if (sc->sc_mem_res)
|
|
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
|
|
mtx_destroy(&sc->sc_mtx);
|
|
|
|
return (ENXIO);
|
|
}
|
|
|
|
static int
|
|
a10_gpio_detach(device_t dev)
|
|
{
|
|
|
|
return (EBUSY);
|
|
}
|
|
|
|
static phandle_t
|
|
a10_gpio_get_node(device_t dev, device_t bus)
|
|
{
|
|
|
|
/* We only have one child, the GPIO bus, which needs our own node. */
|
|
return (ofw_bus_get_node(dev));
|
|
}
|
|
|
|
static int
|
|
a10_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells,
|
|
pcell_t *gpios, uint32_t *pin, uint32_t *flags)
|
|
{
|
|
struct a10_gpio_softc *sc;
|
|
int i;
|
|
|
|
sc = device_get_softc(bus);
|
|
|
|
/* The GPIO pins are mapped as: <gpio-phandle bank pin flags>. */
|
|
for (i = 0; i < sc->padconf->npins; i++)
|
|
if (sc->padconf->pins[i].port == gpios[0] &&
|
|
sc->padconf->pins[i].pin == gpios[1]) {
|
|
*pin = i;
|
|
break;
|
|
}
|
|
*flags = gpios[gcells - 1];
|
|
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t a10_gpio_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, a10_gpio_probe),
|
|
DEVMETHOD(device_attach, a10_gpio_attach),
|
|
DEVMETHOD(device_detach, a10_gpio_detach),
|
|
|
|
/* GPIO protocol */
|
|
DEVMETHOD(gpio_get_bus, a10_gpio_get_bus),
|
|
DEVMETHOD(gpio_pin_max, a10_gpio_pin_max),
|
|
DEVMETHOD(gpio_pin_getname, a10_gpio_pin_getname),
|
|
DEVMETHOD(gpio_pin_getflags, a10_gpio_pin_getflags),
|
|
DEVMETHOD(gpio_pin_getcaps, a10_gpio_pin_getcaps),
|
|
DEVMETHOD(gpio_pin_setflags, a10_gpio_pin_setflags),
|
|
DEVMETHOD(gpio_pin_get, a10_gpio_pin_get),
|
|
DEVMETHOD(gpio_pin_set, a10_gpio_pin_set),
|
|
DEVMETHOD(gpio_pin_toggle, a10_gpio_pin_toggle),
|
|
DEVMETHOD(gpio_map_gpios, a10_gpio_map_gpios),
|
|
|
|
/* ofw_bus interface */
|
|
DEVMETHOD(ofw_bus_get_node, a10_gpio_get_node),
|
|
|
|
/* fdt_pinctrl interface */
|
|
DEVMETHOD(fdt_pinctrl_configure,aw_fdt_configure_pins),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static devclass_t a10_gpio_devclass;
|
|
|
|
static driver_t a10_gpio_driver = {
|
|
"gpio",
|
|
a10_gpio_methods,
|
|
sizeof(struct a10_gpio_softc),
|
|
};
|
|
|
|
EARLY_DRIVER_MODULE(a10_gpio, simplebus, a10_gpio_driver, a10_gpio_devclass, 0, 0,
|
|
BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
|