445 lines
11 KiB
C
445 lines
11 KiB
C
/*-
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* Copyright (c) 2016 Stanislav Galabov.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <machine/fdt.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/fdt/fdt_clock.h>
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#include <mips/mediatek/fdt_reset.h>
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#include <mips/mediatek/mtk_sysctl.h>
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#include <mips/mediatek/mtk_soc.h>
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static uint32_t mtk_soc_socid = MTK_SOC_UNKNOWN;
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static uint32_t mtk_soc_uartclk = 0;
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static uint32_t mtk_soc_cpuclk = MTK_CPU_CLK_880MHZ;
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static uint32_t mtk_soc_timerclk = MTK_CPU_CLK_880MHZ / 2;
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static const struct ofw_compat_data compat_data[] = {
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{ "ralink,rt3050-soc", MTK_SOC_RT3050 },
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{ "ralink,rt3052-soc", MTK_SOC_RT3052 },
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{ "ralink,rt3350-soc", MTK_SOC_RT3350 },
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{ "ralink,rt3352-soc", MTK_SOC_RT3352 },
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{ "ralink,rt3662-soc", MTK_SOC_RT3662 },
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{ "ralink,rt3883-soc", MTK_SOC_RT3883 },
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{ "ralink,rt5350-soc", MTK_SOC_RT5350 },
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{ "ralink,mtk7620a-soc", MTK_SOC_MT7620A },
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{ "ralink,mt7620a-soc", MTK_SOC_MT7620A },
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{ "ralink,mtk7620n-soc", MTK_SOC_MT7620N },
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{ "ralink,mt7620n-soc", MTK_SOC_MT7620N },
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{ "mediatek,mtk7621-soc", MTK_SOC_MT7621 },
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{ "mediatek,mt7621-soc", MTK_SOC_MT7621 },
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{ "ralink,mt7621-soc", MTK_SOC_MT7621 },
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{ "ralink,mtk7621-soc", MTK_SOC_MT7621 },
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{ "ralink,mtk7628an-soc", MTK_SOC_MT7628 },
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{ "mediatek,mt7628an-soc", MTK_SOC_MT7628 },
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{ "ralink,mtk7688-soc", MTK_SOC_MT7688 },
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/* Sentinel */
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{ NULL, MTK_SOC_UNKNOWN },
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};
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static uint32_t
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mtk_detect_cpuclk_rt305x(bus_space_tag_t bst, bus_space_handle_t bsh)
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{
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uint32_t val;
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val = bus_space_read_4(bst, bsh, SYSCTL_CHIPID0_3);
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if (val == RT3350_CHIPID0_3)
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return (MTK_CPU_CLK_320MHZ);
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val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG);
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val >>= RT305X_CPU_CLKSEL_OFF;
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val &= RT305X_CPU_CLKSEL_MSK;
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return ((val == 0) ? MTK_CPU_CLK_320MHZ : MTK_CPU_CLK_384MHZ);
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}
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static uint32_t
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mtk_detect_cpuclk_rt3352(bus_space_tag_t bst, bus_space_handle_t bsh)
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{
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uint32_t val;
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val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG);
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val >>= RT3352_CPU_CLKSEL_OFF;
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val &= RT3352_CPU_CLKSEL_MSK;
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if (val)
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return (MTK_CPU_CLK_400MHZ);
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return (MTK_CPU_CLK_384MHZ);
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}
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static uint32_t
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mtk_detect_cpuclk_rt3883(bus_space_tag_t bst, bus_space_handle_t bsh)
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{
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uint32_t val;
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val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG);
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val >>= RT3883_CPU_CLKSEL_OFF;
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val &= RT3883_CPU_CLKSEL_MSK;
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switch (val) {
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case 0:
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return (MTK_CPU_CLK_250MHZ);
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case 1:
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return (MTK_CPU_CLK_384MHZ);
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case 2:
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return (MTK_CPU_CLK_480MHZ);
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case 3:
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return (MTK_CPU_CLK_500MHZ);
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}
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/* Never reached */
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return (0);
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}
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static uint32_t
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mtk_detect_cpuclk_rt5350(bus_space_tag_t bst, bus_space_handle_t bsh)
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{
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uint32_t val1, val2;
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val1 = val2 = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG);
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val1 >>= RT5350_CPU_CLKSEL_OFF1;
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val2 >>= RT5350_CPU_CLKSEL_OFF2;
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val1 &= RT5350_CPU_CLKSEL_MSK;
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val2 &= RT5350_CPU_CLKSEL_MSK;
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val1 |= (val2 << 1);
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switch (val1) {
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case 0:
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return (MTK_CPU_CLK_360MHZ);
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case 1:
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/* Reserved value, but we return UNKNOWN */
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return (MTK_CPU_CLK_UNKNOWN);
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case 2:
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return (MTK_CPU_CLK_320MHZ);
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case 3:
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return (MTK_CPU_CLK_300MHZ);
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}
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/* Never reached */
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return (0);
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}
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static uint32_t
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mtk_detect_cpuclk_mt7620(bus_space_tag_t bst, bus_space_handle_t bsh)
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{
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uint32_t val, mul, div, res;
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val = bus_space_read_4(bst, bsh, SYSCTL_MT7620_CPLL_CFG1);
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if (val & MT7620_CPU_CLK_AUX0)
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return (MTK_CPU_CLK_480MHZ);
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val = bus_space_read_4(bst, bsh, SYSCTL_MT7620_CPLL_CFG0);
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if (!(val & MT7620_CPLL_SW_CFG))
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return (MTK_CPU_CLK_600MHZ);
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mul = MT7620_PLL_MULT_RATIO_BASE + ((val >> MT7620_PLL_MULT_RATIO_OFF) &
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MT7620_PLL_MULT_RATIO_MSK);
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div = (val >> MT7620_PLL_DIV_RATIO_OFF) & MT7620_PLL_DIV_RATIO_MSK;
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if (div != MT7620_PLL_DIV_RATIO_MSK)
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div += MT7620_PLL_DIV_RATIO_BASE;
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else
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div = MT7620_PLL_DIV_RATIO_MAX;
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res = (MT7620_XTAL_40 * mul) / div;
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return (MTK_MHZ(res));
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}
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static uint32_t
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mtk_detect_cpuclk_mt7621(bus_space_tag_t bst, bus_space_handle_t bsh)
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{
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uint32_t val, div, res;
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val = bus_space_read_4(bst, bsh, SYSCTL_CLKCFG0);
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if (val & MT7621_USES_MEMDIV) {
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div = bus_space_read_4(bst, bsh, MTK_MT7621_CLKDIV_REG);
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div >>= MT7621_MEMDIV_OFF;
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div &= MT7621_MEMDIV_MSK;
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div += MT7621_MEMDIV_BASE;
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val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG);
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val >>= MT7621_CLKSEL_OFF;
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val &= MT7621_CLKSEL_MSK;
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if (val >= MT7621_CLKSEL_25MHZ_VAL)
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res = div * MT7621_CLKSEL_25MHZ;
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else if (val >= MT7621_CLKSEL_20MHZ_VAL)
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res = div * MT7621_CLKSEL_20MHZ;
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else
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res = div * 0; /* XXX: not sure about this */
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} else {
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val = bus_space_read_4(bst, bsh, SYSCTL_CUR_CLK_STS);
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div = (val >> MT7621_CLK_STS_DIV_OFF) & MT7621_CLK_STS_MSK;
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val &= MT7621_CLK_STS_MSK;
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res = (MT7621_CLK_STS_BASE * val) / div;
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}
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return (MTK_MHZ(res));
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}
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static uint32_t
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mtk_detect_cpuclk_mt7628(bus_space_tag_t bst, bus_space_handle_t bsh)
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{
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uint32_t val;
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val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG);
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val >>= MT7628_CPU_CLKSEL_OFF;
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val &= MT7628_CPU_CLKSEL_MSK;
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if (val)
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return (MTK_CPU_CLK_580MHZ);
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return (MTK_CPU_CLK_575MHZ);
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}
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void
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mtk_soc_try_early_detect(void)
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{
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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uint32_t base;
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phandle_t node;
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int i;
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if ((node = OF_finddevice("/")) == -1)
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return;
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for (i = 0; compat_data[i].ocd_str != NULL; i++) {
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if (fdt_is_compatible(node, compat_data[i].ocd_str)) {
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mtk_soc_socid = compat_data[i].ocd_data;
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break;
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}
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}
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if (mtk_soc_socid == MTK_SOC_UNKNOWN) {
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/* We don't know the SoC, so we don't know how to get clocks */
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return;
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}
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bst = fdtbus_bs_tag;
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if (mtk_soc_socid == MTK_SOC_MT7621)
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base = MTK_MT7621_BASE;
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else
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base = MTK_DEFAULT_BASE;
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if (bus_space_map(bst, base, MTK_DEFAULT_SIZE, 0, &bsh))
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return;
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/* First, figure out the CPU clock */
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switch (mtk_soc_socid) {
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case MTK_SOC_RT3050: /* fallthrough */
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case MTK_SOC_RT3052:
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case MTK_SOC_RT3350:
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mtk_soc_cpuclk = mtk_detect_cpuclk_rt305x(bst, bsh);
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break;
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case MTK_SOC_RT3352:
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mtk_soc_cpuclk = mtk_detect_cpuclk_rt3352(bst, bsh);
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break;
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case MTK_SOC_RT3662: /* fallthrough */
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case MTK_SOC_RT3883:
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mtk_soc_cpuclk = mtk_detect_cpuclk_rt3883(bst, bsh);
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break;
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case MTK_SOC_RT5350:
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mtk_soc_cpuclk = mtk_detect_cpuclk_rt5350(bst, bsh);
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break;
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case MTK_SOC_MT7620A: /* fallthrough */
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case MTK_SOC_MT7620N:
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mtk_soc_cpuclk = mtk_detect_cpuclk_mt7620(bst, bsh);
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break;
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case MTK_SOC_MT7621:
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mtk_soc_cpuclk = mtk_detect_cpuclk_mt7621(bst, bsh);
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break;
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case MTK_SOC_MT7628: /* fallthrough */
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case MTK_SOC_MT7688:
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mtk_soc_cpuclk = mtk_detect_cpuclk_mt7628(bst, bsh);
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break;
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default:
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/* We don't know the SoC, so we can't find the CPU clock */
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break;
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}
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/* Now figure out the timer clock */
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if (mtk_soc_socid == MTK_SOC_MT7621) {
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#ifdef notyet
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/*
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* We use the GIC timer for timing source and its clock freq is
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* the same as the CPU's clock freq
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*/
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mtk_soc_timerclk = mtk_soc_cpuclk;
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#else
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/*
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* When GIC timer and MIPS timer are ready to co-exist and
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* GIC timer is actually implemented, we need to switch to it.
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* Until then we use a fake GIC timer, which is actually a
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* normal MIPS ticker, so the timer clock is half the CPU clock
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*/
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mtk_soc_timerclk = mtk_soc_cpuclk / 2;
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#endif
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} else {
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/*
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* We use the MIPS ticker for the rest for now, so
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* the CPU clock is divided by 2
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*/
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mtk_soc_timerclk = mtk_soc_cpuclk / 2;
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}
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switch (mtk_soc_socid) {
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case MTK_SOC_RT3350: /* fallthrough */
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case MTK_SOC_RT3050: /* fallthrough */
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case MTK_SOC_RT3052:
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/* UART clock is CPU clock / 3 */
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mtk_soc_uartclk = mtk_soc_cpuclk / MTK_UARTDIV_3;
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break;
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case MTK_SOC_RT3352: /* fallthrough */
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case MTK_SOC_RT3662: /* fallthrough */
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case MTK_SOC_RT3883: /* fallthrough */
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case MTK_SOC_RT5350: /* fallthrough */
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case MTK_SOC_MT7620A: /* fallthrough */
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case MTK_SOC_MT7620N: /* fallthrough */
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case MTK_SOC_MT7628: /* fallthrough */
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case MTK_SOC_MT7688:
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/* UART clock is always 40MHz */
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mtk_soc_uartclk = MTK_UART_CLK_40MHZ;
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break;
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case MTK_SOC_MT7621:
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/* UART clock is always 50MHz */
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mtk_soc_uartclk = MTK_UART_CLK_50MHZ;
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break;
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default:
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/* We don't know the SoC, so we don't know the UART clock */
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break;
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}
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bus_space_unmap(bst, bsh, MTK_DEFAULT_SIZE);
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}
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uint32_t
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mtk_soc_get_uartclk(void)
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{
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return mtk_soc_uartclk;
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}
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uint32_t
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mtk_soc_get_cpuclk(void)
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{
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return mtk_soc_cpuclk;
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}
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uint32_t
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mtk_soc_get_timerclk(void)
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{
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return mtk_soc_timerclk;
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}
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uint32_t
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mtk_soc_get_socid(void)
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{
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return mtk_soc_socid;
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}
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/*
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* The following are generic reset and clock functions
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*/
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/* Default reset time is 100ms */
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#define DEFAULT_RESET_TIME 100000
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int
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mtk_soc_reset_device(device_t dev)
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{
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int res;
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res = fdt_reset_assert_all(dev);
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if (res == 0) {
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DELAY(DEFAULT_RESET_TIME);
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res = fdt_reset_deassert_all(dev);
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if (res == 0)
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DELAY(DEFAULT_RESET_TIME);
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}
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return (res);
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}
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int
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mtk_soc_stop_clock(device_t dev)
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{
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return (fdt_clock_disable_all(dev));
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}
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int
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mtk_soc_start_clock(device_t dev)
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{
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return (fdt_clock_enable_all(dev));
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}
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int
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mtk_soc_assert_reset(device_t dev)
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{
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return (fdt_reset_assert_all(dev));
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}
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int
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mtk_soc_deassert_reset(device_t dev)
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{
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return (fdt_reset_deassert_all(dev));
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}
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void
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mtk_soc_reset(void)
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{
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mtk_sysctl_clr_set(SYSCTL_RSTCTRL, 0, 1);
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mtk_sysctl_clr_set(SYSCTL_RSTCTRL, 1, 0);
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}
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