543 lines
14 KiB
C
543 lines
14 KiB
C
/*-
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* Copyright (c) 2009 Neelkanth Natu
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/types.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/pcpu.h>
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#include <sys/smp.h>
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#include <vm/vm.h>
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#include <vm/vm_param.h>
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#include <vm/vm_kern.h>
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#include <vm/vm_extern.h>
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#include <vm/pmap.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcib_private.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include "pcib_if.h"
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#include "sb_bus_space.h"
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#include "sb_scd.h"
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__FBSDID("$FreeBSD$");
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static struct {
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vm_offset_t vaddr;
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vm_paddr_t paddr;
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} zbpci_config_space[MAXCPU];
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static const vm_paddr_t CFG_PADDR_BASE = 0xFE000000;
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static const u_long PCI_IOSPACE_ADDR = 0xFC000000;
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static const u_long PCI_IOSPACE_SIZE = 0x02000000;
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#define PCI_MATCH_BYTE_LANES_START 0x40000000
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#define PCI_MATCH_BYTE_LANES_END 0x5FFFFFFF
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#define PCI_MATCH_BYTE_LANES_SIZE 0x20000000
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#define PCI_MATCH_BIT_LANES_MASK (1 << 29)
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#define PCI_MATCH_BIT_LANES_START 0x60000000
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#define PCI_MATCH_BIT_LANES_END 0x7FFFFFFF
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#define PCI_MATCH_BIT_LANES_SIZE 0x20000000
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static struct rman port_rman;
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static int
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zbpci_probe(device_t dev)
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{
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device_set_desc(dev, "Broadcom/Sibyte PCI I/O Bridge");
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return (0);
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}
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static int
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zbpci_attach(device_t dev)
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{
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int n, rid, size;
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vm_offset_t va;
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struct resource *res;
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/*
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* Reserve the physical memory window used to map PCI I/O space.
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*/
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rid = 0;
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res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
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PCI_IOSPACE_ADDR,
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PCI_IOSPACE_ADDR + PCI_IOSPACE_SIZE - 1,
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PCI_IOSPACE_SIZE, 0);
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if (res == NULL)
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panic("Cannot allocate resource for PCI I/O space mapping.");
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port_rman.rm_start = 0;
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port_rman.rm_end = PCI_IOSPACE_SIZE - 1;
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port_rman.rm_type = RMAN_ARRAY;
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port_rman.rm_descr = "PCI I/O ports";
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if (rman_init(&port_rman) != 0 ||
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rman_manage_region(&port_rman, 0, PCI_IOSPACE_SIZE - 1) != 0)
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panic("%s: port_rman", __func__);
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/*
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* Reserve the physical memory that is used to read/write to the
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* pci config space but don't activate it. We are using a page worth
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* of KVA as a window over this region.
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*/
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rid = 1;
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size = (PCI_BUSMAX + 1) * (PCI_SLOTMAX + 1) * (PCI_FUNCMAX + 1) * 256;
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res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, CFG_PADDR_BASE,
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CFG_PADDR_BASE + size - 1, size, 0);
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if (res == NULL)
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panic("Cannot allocate resource for config space accesses.");
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/*
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* Allocate the entire "match bit lanes" address space.
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*/
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#if _BYTE_ORDER == _BIG_ENDIAN
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rid = 2;
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res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
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PCI_MATCH_BIT_LANES_START,
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PCI_MATCH_BIT_LANES_END,
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PCI_MATCH_BIT_LANES_SIZE, 0);
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if (res == NULL)
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panic("Cannot allocate resource for pci match bit lanes.");
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#endif /* _BYTE_ORDER ==_BIG_ENDIAN */
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/*
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* Allocate KVA for accessing PCI config space.
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*/
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va = kva_alloc(PAGE_SIZE * mp_ncpus);
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if (va == 0) {
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device_printf(dev, "Cannot allocate virtual addresses for "
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"config space access.\n");
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return (ENOMEM);
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}
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for (n = 0; n < mp_ncpus; ++n)
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zbpci_config_space[n].vaddr = va + n * PAGE_SIZE;
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/*
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* Sibyte has the PCI bus hierarchy rooted at bus 0 and HT-PCI
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* hierarchy rooted at bus 1.
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*/
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if (device_add_child(dev, "pci", 0) == NULL)
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panic("zbpci_attach: could not add pci bus 0.\n");
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if (device_add_child(dev, "pci", 1) == NULL)
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panic("zbpci_attach: could not add pci bus 1.\n");
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if (bootverbose)
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device_printf(dev, "attached.\n");
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return (bus_generic_attach(dev));
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}
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static struct resource *
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zbpci_alloc_resource(device_t bus, device_t child, int type, int *rid,
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rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
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{
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struct resource *res;
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/*
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* Handle PCI I/O port resources here and pass everything else to nexus.
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*/
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if (type != SYS_RES_IOPORT) {
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res = bus_generic_alloc_resource(bus, child, type, rid,
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start, end, count, flags);
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return (res);
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}
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res = rman_reserve_resource(&port_rman, start, end, count,
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flags, child);
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if (res == NULL)
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return (NULL);
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rman_set_rid(res, *rid);
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/* Activate the resource is requested */
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if (flags & RF_ACTIVE) {
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if (bus_activate_resource(child, type, *rid, res) != 0) {
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rman_release_resource(res);
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return (NULL);
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}
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}
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return (res);
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}
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static int
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zbpci_activate_resource(device_t bus, device_t child, int type, int rid,
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struct resource *res)
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{
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int error;
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void *vaddr;
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u_long orig_paddr, paddr, psize;
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paddr = rman_get_start(res);
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psize = rman_get_size(res);
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orig_paddr = paddr;
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#if _BYTE_ORDER == _BIG_ENDIAN
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/*
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* The CFE allocates PCI memory resources that map to the
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* "match byte lanes" address space. This address space works
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* best for DMA transfers because it does not do any automatic
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* byte swaps when data crosses the pci-cpu interface.
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*
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* This also makes it sub-optimal for accesses to PCI device
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* registers because it exposes the little-endian nature of
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* the PCI bus to the big-endian CPU. The Sibyte has another
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* address window called the "match bit lanes" window which
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* automatically swaps bytes when data crosses the pci-cpu
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* interface.
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*
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* We "assume" that any bus_space memory accesses done by the
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* CPU to a PCI device are register/configuration accesses and
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* are done through the "match bit lanes" window. Any DMA
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* transfers will continue to be through the "match byte lanes"
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* window because the PCI BAR registers will not be changed.
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*/
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if (type == SYS_RES_MEMORY) {
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if (paddr >= PCI_MATCH_BYTE_LANES_START &&
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paddr + psize - 1 <= PCI_MATCH_BYTE_LANES_END) {
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paddr |= PCI_MATCH_BIT_LANES_MASK;
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rman_set_start(res, paddr);
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rman_set_end(res, paddr + psize - 1);
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}
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}
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#endif
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if (type != SYS_RES_IOPORT) {
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error = bus_generic_activate_resource(bus, child, type,
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rid, res);
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#if _BYTE_ORDER == _BIG_ENDIAN
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if (type == SYS_RES_MEMORY) {
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rman_set_start(res, orig_paddr);
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rman_set_end(res, orig_paddr + psize - 1);
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}
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#endif
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return (error);
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}
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/*
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* Map the I/O space resource through the memory window starting
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* at PCI_IOSPACE_ADDR.
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*/
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vaddr = pmap_mapdev(paddr + PCI_IOSPACE_ADDR, psize);
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rman_set_virtual(res, vaddr);
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rman_set_bustag(res, mips_bus_space_generic);
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rman_set_bushandle(res, (bus_space_handle_t)vaddr);
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return (rman_activate_resource(res));
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}
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static int
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zbpci_release_resource(device_t bus, device_t child, int type, int rid,
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struct resource *r)
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{
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int error;
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if (type != SYS_RES_IOPORT)
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return (bus_generic_release_resource(bus, child, type, rid, r));
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if (rman_get_flags(r) & RF_ACTIVE) {
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error = bus_deactivate_resource(child, type, rid, r);
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if (error)
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return (error);
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}
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return (rman_release_resource(r));
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}
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static int
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zbpci_deactivate_resource(device_t bus, device_t child, int type, int rid,
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struct resource *r)
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{
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vm_offset_t va;
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if (type != SYS_RES_IOPORT) {
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return (bus_generic_deactivate_resource(bus, child, type,
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rid, r));
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}
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va = (vm_offset_t)rman_get_virtual(r);
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pmap_unmapdev(va, rman_get_size(r));
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return (rman_deactivate_resource(r));
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}
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static int
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zbpci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
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{
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switch (which) {
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case PCIB_IVAR_DOMAIN:
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*result = 0; /* single PCI domain */
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return (0);
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case PCIB_IVAR_BUS:
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*result = device_get_unit(child); /* PCI bus 0 or 1 */
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return (0);
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default:
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return (ENOENT);
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}
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}
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/*
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* We rely on the CFE to have configured the intline correctly to point to
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* one of PCI-A/PCI-B/PCI-C/PCI-D in the interupt mapper.
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*/
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static int
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zbpci_route_interrupt(device_t pcib, device_t dev, int pin)
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{
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return (PCI_INVALID_IRQ);
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}
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/*
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* This function is expected to be called in a critical section since it
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* changes the per-cpu pci config space va-to-pa mappings.
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*/
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static vm_offset_t
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zbpci_config_space_va(int bus, int slot, int func, int reg, int bytes)
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{
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int cpu;
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vm_offset_t va_page;
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vm_paddr_t pa, pa_page;
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if (bus <= PCI_BUSMAX && slot <= PCI_SLOTMAX && func <= PCI_FUNCMAX &&
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reg <= PCI_REGMAX && (bytes == 1 || bytes == 2 || bytes == 4) &&
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((reg & (bytes - 1)) == 0)) {
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cpu = PCPU_GET(cpuid);
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va_page = zbpci_config_space[cpu].vaddr;
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pa = CFG_PADDR_BASE |
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(bus << 16) | (slot << 11) | (func << 8) | reg;
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#if _BYTE_ORDER == _BIG_ENDIAN
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pa = pa ^ (4 - bytes);
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#endif
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pa_page = rounddown2(pa, PAGE_SIZE);
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if (zbpci_config_space[cpu].paddr != pa_page) {
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pmap_kremove(va_page);
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pmap_kenter_attr(va_page, pa_page, PTE_C_UNCACHED);
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zbpci_config_space[cpu].paddr = pa_page;
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}
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return (va_page + (pa - pa_page));
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} else {
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return (0);
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}
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}
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static uint32_t
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zbpci_read_config(device_t dev, u_int b, u_int s, u_int f, u_int r, int w)
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{
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uint32_t data;
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vm_offset_t va;
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critical_enter();
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va = zbpci_config_space_va(b, s, f, r, w);
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if (va == 0) {
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panic("zbpci_read_config: invalid %d/%d/%d[%d] %d\n",
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b, s, f, r, w);
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}
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switch (w) {
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case 4:
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data = *(uint32_t *)va;
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break;
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case 2:
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data = *(uint16_t *)va;
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break;
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case 1:
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data = *(uint8_t *)va;
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break;
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default:
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panic("zbpci_read_config: invalid width %d\n", w);
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}
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critical_exit();
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return (data);
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}
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static void
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zbpci_write_config(device_t d, u_int b, u_int s, u_int f, u_int r,
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uint32_t data, int w)
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{
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vm_offset_t va;
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critical_enter();
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va = zbpci_config_space_va(b, s, f, r, w);
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if (va == 0) {
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panic("zbpci_write_config: invalid %d/%d/%d[%d] %d/%d\n",
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b, s, f, r, data, w);
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}
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switch (w) {
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case 4:
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*(uint32_t *)va = data;
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break;
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case 2:
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*(uint16_t *)va = data;
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break;
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case 1:
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*(uint8_t *)va = data;
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break;
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default:
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panic("zbpci_write_config: invalid width %d\n", w);
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}
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critical_exit();
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}
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static device_method_t zbpci_methods[] ={
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/* Device interface */
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DEVMETHOD(device_probe, zbpci_probe),
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DEVMETHOD(device_attach, zbpci_attach),
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DEVMETHOD(device_detach, bus_generic_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD(device_suspend, bus_generic_suspend),
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DEVMETHOD(device_resume, bus_generic_resume),
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/* Bus interface */
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DEVMETHOD(bus_read_ivar, zbpci_read_ivar),
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DEVMETHOD(bus_write_ivar, bus_generic_write_ivar),
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DEVMETHOD(bus_alloc_resource, zbpci_alloc_resource),
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DEVMETHOD(bus_activate_resource, zbpci_activate_resource),
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DEVMETHOD(bus_deactivate_resource, zbpci_deactivate_resource),
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DEVMETHOD(bus_release_resource, zbpci_release_resource),
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DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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DEVMETHOD(bus_add_child, bus_generic_add_child),
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/* pcib interface */
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DEVMETHOD(pcib_maxslots, pcib_maxslots),
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DEVMETHOD(pcib_read_config, zbpci_read_config),
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DEVMETHOD(pcib_write_config, zbpci_write_config),
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DEVMETHOD(pcib_route_interrupt, zbpci_route_interrupt),
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{ 0, 0 }
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};
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/*
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* The "zbpci" class inherits from the "pcib" base class. Therefore in
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* addition to drivers that belong to the "zbpci" class we will also
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* consider drivers belonging to the "pcib" when probing children of
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* "zbpci".
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*/
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DEFINE_CLASS_1(zbpci, zbpci_driver, zbpci_methods, 0, pcib_driver);
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static devclass_t zbpci_devclass;
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DRIVER_MODULE(zbpci, zbbus, zbpci_driver, zbpci_devclass, 0, 0);
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/*
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* Big endian bus space routines
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*/
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#if _BYTE_ORDER == _BIG_ENDIAN
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/*
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* The CPU correctly deals with the big-endian to little-endian swap if
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* we are accessing 4 bytes at a time. However if we want to read 1 or 2
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* bytes then we need to fudge the address generated by the CPU such that
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* it generates the right byte enables on the PCI bus.
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*/
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static bus_addr_t
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sb_match_bit_lane_addr(bus_addr_t addr, int bytes)
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{
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vm_offset_t pa;
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pa = vtophys(addr);
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if (pa >= PCI_MATCH_BIT_LANES_START && pa <= PCI_MATCH_BIT_LANES_END)
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return (addr ^ (4 - bytes));
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else
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return (addr);
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}
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uint8_t
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sb_big_endian_read8(bus_addr_t addr)
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{
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bus_addr_t addr2;
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addr2 = sb_match_bit_lane_addr(addr, 1);
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return (readb(addr2));
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}
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uint16_t
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sb_big_endian_read16(bus_addr_t addr)
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{
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bus_addr_t addr2;
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addr2 = sb_match_bit_lane_addr(addr, 2);
|
|
return (readw(addr2));
|
|
}
|
|
|
|
uint32_t
|
|
sb_big_endian_read32(bus_addr_t addr)
|
|
{
|
|
bus_addr_t addr2;
|
|
|
|
addr2 = sb_match_bit_lane_addr(addr, 4);
|
|
return (readl(addr2));
|
|
}
|
|
|
|
void
|
|
sb_big_endian_write8(bus_addr_t addr, uint8_t val)
|
|
{
|
|
bus_addr_t addr2;
|
|
|
|
addr2 = sb_match_bit_lane_addr(addr, 1);
|
|
writeb(addr2, val);
|
|
}
|
|
|
|
void
|
|
sb_big_endian_write16(bus_addr_t addr, uint16_t val)
|
|
{
|
|
bus_addr_t addr2;
|
|
|
|
addr2 = sb_match_bit_lane_addr(addr, 2);
|
|
writew(addr2, val);
|
|
}
|
|
|
|
void
|
|
sb_big_endian_write32(bus_addr_t addr, uint32_t val)
|
|
{
|
|
bus_addr_t addr2;
|
|
|
|
addr2 = sb_match_bit_lane_addr(addr, 4);
|
|
writel(addr2, val);
|
|
}
|
|
#endif /* _BIG_ENDIAN */
|