158 lines
4.0 KiB
C
158 lines
4.0 KiB
C
/*-
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* Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
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* reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* NETLOGIC_BSD
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* $FreeBSD$
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*/
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#ifndef __NLM_BOARD_H__
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#define __NLM_BOARD_H__
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#define XLP_NAE_NBLOCKS 5
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#define XLP_NAE_NPORTS 4
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/*
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* EVP board EEPROM info
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*/
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#define EEPROM_I2CBUS 1
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#define EEPROM_I2CADDR 0xAE
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#define EEPROM_SIZE 48
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#define EEPROM_MACADDR_OFFSET 2
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/* used if there is no FDT */
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#define BOARD_CONSOLE_SPEED 115200
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#define BOARD_CONSOLE_UART 0
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/*
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* EVP board CPLD chip select and daughter card info field
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*/
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#define XLP_EVB_CPLD_CHIPSELECT 2
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#define DCARD_ILAKEN 0x0
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#define DCARD_SGMII 0x1
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#define DCARD_XAUI 0x2
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#define DCARD_NOT_PRSNT 0x3
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#if !defined(LOCORE) && !defined(__ASSEMBLY__)
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/*
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* NAE configuration
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*/
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struct xlp_port_ivars {
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int port;
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int block;
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int node;
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int type;
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int phy_addr;
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int mdio_bus;
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int loopback_mode;
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int num_channels;
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int free_desc_sizes;
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int num_free_descs;
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int pseq_fifo_size;
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int iface_fifo_size;
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int rxbuf_size;
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int rx_slots_reqd;
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int tx_slots_reqd;
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int vlan_pri_en;
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int stg2_fifo_size;
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int eh_fifo_size;
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int frout_fifo_size;
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int ms_fifo_size;
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int pkt_fifo_size;
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int pktlen_fifo_size;
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int max_stg2_offset;
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int max_eh_offset;
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int max_frout_offset;
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int max_ms_offset;
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int max_pmem_offset;
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int stg1_2_credit;
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int stg2_eh_credit;
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int stg2_frout_credit;
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int stg2_ms_credit;
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int hw_parser_en;
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u_int ieee1588_inc_intg;
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u_int ieee1588_inc_den;
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u_int ieee1588_inc_num;
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uint64_t ieee1588_userval;
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uint64_t ieee1588_ptpoff;
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uint64_t ieee1588_tmr1;
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uint64_t ieee1588_tmr2;
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uint64_t ieee1588_tmr3;
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};
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struct xlp_block_ivars {
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int block;
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int type;
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u_int portmask;
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struct xlp_port_ivars port_ivars[XLP_NAE_NPORTS];
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};
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struct xlp_nae_ivars {
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int node;
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int nblocks;
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u_int blockmask;
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u_int ilmask;
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u_int xauimask;
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u_int sgmiimask;
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int freq;
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u_int flow_crc_poly;
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u_int hw_parser_en;
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u_int prepad_en;
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u_int prepad_size; /* size in 16 byte units */
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u_int ieee_1588_en;
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struct xlp_block_ivars block_ivars[XLP_NAE_NBLOCKS];
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};
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struct xlp_board_info {
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u_int nodemask;
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struct xlp_node_info {
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struct xlp_nae_ivars nae_ivars;
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} nodes[XLP_MAX_NODES];
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};
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extern struct xlp_board_info xlp_board_info;
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/* Network configuration */
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int nlm_get_vfbid_mapping(int);
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int nlm_get_poe_distvec(int vec, uint32_t *distvec);
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void xlpge_get_macaddr(uint8_t *macaddr);
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int nlm_board_info_setup(void);
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/* EEPROM & CPLD */
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int nlm_board_eeprom_read(int node, int i2cbus, int addr, int offs,
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uint8_t *buf,int sz);
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uint64_t nlm_board_cpld_base(int node, int chipselect);
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int nlm_board_cpld_majorversion(uint64_t cpldbase);
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int nlm_board_cpld_minorversion(uint64_t cpldbase);
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void nlm_board_cpld_reset(uint64_t cpldbase);
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int nlm_board_cpld_dboard_type(uint64_t cpldbase, int slot);
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#endif
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#endif
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