914 lines
23 KiB
C
914 lines
23 KiB
C
/*
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* Copyright 2015 Andrew Turner.
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* Copyright 2016 Svatopluk Kraus
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/cpuset.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/proc.h>
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#include <sys/rman.h>
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#ifdef SMP
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#include <sys/smp.h>
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#endif
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/resource.h>
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#ifdef SMP
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#include <machine/smp.h>
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#endif
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/ofw_bus.h>
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#ifdef INTRNG
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#include "pic_if.h"
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#else
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#include <arm/broadcom/bcm2835/bcm2836.h>
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#define ARM_LOCAL_BASE 0x40000000
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#define ARM_LOCAL_SIZE 0x00001000
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#define ARM_LOCAL_CONTROL 0x00
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#define ARM_LOCAL_PRESCALER 0x08
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#define PRESCALER_19_2 0x80000000 /* 19.2 MHz */
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#define ARM_LOCAL_INT_TIMER(n) (0x40 + (n) * 4)
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#define ARM_LOCAL_INT_MAILBOX(n) (0x50 + (n) * 4)
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#define ARM_LOCAL_INT_PENDING(n) (0x60 + (n) * 4)
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#define INT_PENDING_MASK 0x011f
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#define MAILBOX0_IRQ 4
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#define MAILBOX0_IRQEN (1 << 0)
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#endif
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#ifdef INTRNG
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#define BCM_LINTC_CONTROL_REG 0x00
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#define BCM_LINTC_PRESCALER_REG 0x08
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#define BCM_LINTC_GPU_ROUTING_REG 0x0c
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#define BCM_LINTC_PMU_ROUTING_SET_REG 0x10
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#define BCM_LINTC_PMU_ROUTING_CLR_REG 0x14
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#define BCM_LINTC_TIMER_CFG_REG(n) (0x40 + (n) * 4)
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#define BCM_LINTC_MBOX_CFG_REG(n) (0x50 + (n) * 4)
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#define BCM_LINTC_PENDING_REG(n) (0x60 + (n) * 4)
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#define BCM_LINTC_MBOX0_SET_REG(n) (0x80 + (n) * 16)
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#define BCM_LINTC_MBOX1_SET_REG(n) (0x84 + (n) * 16)
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#define BCM_LINTC_MBOX2_SET_REG(n) (0x88 + (n) * 16)
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#define BCM_LINTC_MBOX3_SET_REG(n) (0x8C + (n) * 16)
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#define BCM_LINTC_MBOX0_CLR_REG(n) (0xC0 + (n) * 16)
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#define BCM_LINTC_MBOX1_CLR_REG(n) (0xC4 + (n) * 16)
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#define BCM_LINTC_MBOX2_CLR_REG(n) (0xC8 + (n) * 16)
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#define BCM_LINTC_MBOX3_CLR_REG(n) (0xCC + (n) * 16)
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/* Prescaler Register */
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#define BCM_LINTC_PSR_19_2 0x80000000 /* 19.2 MHz */
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/* GPU Interrupt Routing Register */
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#define BCM_LINTC_GIRR_IRQ_CORE(n) (n)
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#define BCM_LINTC_GIRR_FIQ_CORE(n) ((n) << 2)
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/* PMU Interrupt Routing Register */
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#define BCM_LINTC_PIRR_IRQ_EN_CORE(n) (1 << (n))
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#define BCM_LINTC_PIRR_FIQ_EN_CORE(n) (1 << ((n) + 4))
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/* Timer Config Register */
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#define BCM_LINTC_TCR_IRQ_EN_TIMER(n) (1 << (n))
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#define BCM_LINTC_TCR_FIQ_EN_TIMER(n) (1 << ((n) + 4))
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/* MBOX Config Register */
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#define BCM_LINTC_MCR_IRQ_EN_MBOX(n) (1 << (n))
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#define BCM_LINTC_MCR_FIQ_EN_MBOX(n) (1 << ((n) + 4))
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#define BCM_LINTC_CNTPSIRQ_IRQ 0
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#define BCM_LINTC_CNTPNSIRQ_IRQ 1
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#define BCM_LINTC_CNTHPIRQ_IRQ 2
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#define BCM_LINTC_CNTVIRQ_IRQ 3
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#define BCM_LINTC_MBOX0_IRQ 4
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#define BCM_LINTC_MBOX1_IRQ 5
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#define BCM_LINTC_MBOX2_IRQ 6
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#define BCM_LINTC_MBOX3_IRQ 7
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#define BCM_LINTC_GPU_IRQ 8
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#define BCM_LINTC_PMU_IRQ 9
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#define BCM_LINTC_AXI_IRQ 10
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#define BCM_LINTC_LTIMER_IRQ 11
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#define BCM_LINTC_NIRQS 12
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#define BCM_LINTC_TIMER0_IRQ BCM_LINTC_CNTPSIRQ_IRQ
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#define BCM_LINTC_TIMER1_IRQ BCM_LINTC_CNTPNSIRQ_IRQ
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#define BCM_LINTC_TIMER2_IRQ BCM_LINTC_CNTHPIRQ_IRQ
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#define BCM_LINTC_TIMER3_IRQ BCM_LINTC_CNTVIRQ_IRQ
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#define BCM_LINTC_TIMER0_IRQ_MASK (1 << BCM_LINTC_TIMER0_IRQ)
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#define BCM_LINTC_TIMER1_IRQ_MASK (1 << BCM_LINTC_TIMER1_IRQ)
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#define BCM_LINTC_TIMER2_IRQ_MASK (1 << BCM_LINTC_TIMER2_IRQ)
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#define BCM_LINTC_TIMER3_IRQ_MASK (1 << BCM_LINTC_TIMER3_IRQ)
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#define BCM_LINTC_MBOX0_IRQ_MASK (1 << BCM_LINTC_MBOX0_IRQ)
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#define BCM_LINTC_GPU_IRQ_MASK (1 << BCM_LINTC_GPU_IRQ)
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#define BCM_LINTC_PMU_IRQ_MASK (1 << BCM_LINTC_PMU_IRQ)
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#define BCM_LINTC_UP_PENDING_MASK \
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(BCM_LINTC_TIMER0_IRQ_MASK | \
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BCM_LINTC_TIMER1_IRQ_MASK | \
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BCM_LINTC_TIMER2_IRQ_MASK | \
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BCM_LINTC_TIMER3_IRQ_MASK | \
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BCM_LINTC_GPU_IRQ_MASK | \
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BCM_LINTC_PMU_IRQ_MASK)
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#define BCM_LINTC_SMP_PENDING_MASK \
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(BCM_LINTC_UP_PENDING_MASK | \
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BCM_LINTC_MBOX0_IRQ_MASK)
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#ifdef SMP
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#define BCM_LINTC_PENDING_MASK BCM_LINTC_SMP_PENDING_MASK
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#else
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#define BCM_LINTC_PENDING_MASK BCM_LINTC_UP_PENDING_MASK
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#endif
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struct bcm_lintc_irqsrc {
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struct intr_irqsrc bli_isrc;
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u_int bli_irq;
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union {
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u_int bli_mask; /* for timers */
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u_int bli_value; /* for GPU */
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};
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};
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struct bcm_lintc_softc {
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device_t bls_dev;
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struct mtx bls_mtx;
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struct resource * bls_mem;
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bus_space_tag_t bls_bst;
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bus_space_handle_t bls_bsh;
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struct bcm_lintc_irqsrc bls_isrcs[BCM_LINTC_NIRQS];
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};
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static struct bcm_lintc_softc *bcm_lintc_sc;
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#ifdef SMP
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#define BCM_LINTC_NIPIS 32 /* only mailbox 0 is used for IPI */
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CTASSERT(INTR_IPI_COUNT <= BCM_LINTC_NIPIS);
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#endif
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#define BCM_LINTC_LOCK(sc) mtx_lock_spin(&(sc)->bls_mtx)
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#define BCM_LINTC_UNLOCK(sc) mtx_unlock_spin(&(sc)->bls_mtx)
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#define BCM_LINTC_LOCK_INIT(sc) mtx_init(&(sc)->bls_mtx, \
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device_get_nameunit((sc)->bls_dev), "bmc_local_intc", MTX_SPIN)
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#define BCM_LINTC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->bls_mtx)
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#define bcm_lintc_read_4(sc, reg) \
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bus_space_read_4((sc)->bls_bst, (sc)->bls_bsh, (reg))
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#define bcm_lintc_write_4(sc, reg, val) \
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bus_space_write_4((sc)->bls_bst, (sc)->bls_bsh, (reg), (val))
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static inline void
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bcm_lintc_rwreg_clr(struct bcm_lintc_softc *sc, uint32_t reg,
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uint32_t mask)
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{
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bcm_lintc_write_4(sc, reg, bcm_lintc_read_4(sc, reg) & ~mask);
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}
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static inline void
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bcm_lintc_rwreg_set(struct bcm_lintc_softc *sc, uint32_t reg,
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uint32_t mask)
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{
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bcm_lintc_write_4(sc, reg, bcm_lintc_read_4(sc, reg) | mask);
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}
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static void
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bcm_lintc_timer_mask(struct bcm_lintc_softc *sc, struct bcm_lintc_irqsrc *bli)
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{
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cpuset_t *cpus;
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uint32_t cpu;
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cpus = &bli->bli_isrc.isrc_cpu;
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BCM_LINTC_LOCK(sc);
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for (cpu = 0; cpu < 4; cpu++)
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if (CPU_ISSET(cpu, cpus))
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bcm_lintc_rwreg_clr(sc, BCM_LINTC_TIMER_CFG_REG(cpu),
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bli->bli_mask);
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BCM_LINTC_UNLOCK(sc);
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}
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static void
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bcm_lintc_timer_unmask(struct bcm_lintc_softc *sc, struct bcm_lintc_irqsrc *bli)
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{
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cpuset_t *cpus;
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uint32_t cpu;
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cpus = &bli->bli_isrc.isrc_cpu;
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BCM_LINTC_LOCK(sc);
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for (cpu = 0; cpu < 4; cpu++)
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if (CPU_ISSET(cpu, cpus))
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bcm_lintc_rwreg_set(sc, BCM_LINTC_TIMER_CFG_REG(cpu),
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bli->bli_mask);
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BCM_LINTC_UNLOCK(sc);
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}
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static inline void
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bcm_lintc_gpu_mask(struct bcm_lintc_softc *sc, struct bcm_lintc_irqsrc *bli)
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{
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/* It's accessed just and only by one core. */
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bcm_lintc_write_4(sc, BCM_LINTC_GPU_ROUTING_REG, 0);
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}
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static inline void
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bcm_lintc_gpu_unmask(struct bcm_lintc_softc *sc, struct bcm_lintc_irqsrc *bli)
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{
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/* It's accessed just and only by one core. */
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bcm_lintc_write_4(sc, BCM_LINTC_GPU_ROUTING_REG, bli->bli_value);
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}
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static inline void
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bcm_lintc_pmu_mask(struct bcm_lintc_softc *sc, struct bcm_lintc_irqsrc *bli)
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{
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cpuset_t *cpus;
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uint32_t cpu, mask;
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mask = 0;
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cpus = &bli->bli_isrc.isrc_cpu;
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BCM_LINTC_LOCK(sc);
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for (cpu = 0; cpu < 4; cpu++)
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if (CPU_ISSET(cpu, cpus))
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mask |= BCM_LINTC_PIRR_IRQ_EN_CORE(cpu);
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/* Write-clear register. */
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bcm_lintc_write_4(sc, BCM_LINTC_PMU_ROUTING_CLR_REG, mask);
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BCM_LINTC_UNLOCK(sc);
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}
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static inline void
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bcm_lintc_pmu_unmask(struct bcm_lintc_softc *sc, struct bcm_lintc_irqsrc *bli)
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{
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cpuset_t *cpus;
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uint32_t cpu, mask;
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mask = 0;
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cpus = &bli->bli_isrc.isrc_cpu;
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BCM_LINTC_LOCK(sc);
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for (cpu = 0; cpu < 4; cpu++)
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if (CPU_ISSET(cpu, cpus))
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mask |= BCM_LINTC_PIRR_IRQ_EN_CORE(cpu);
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/* Write-set register. */
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bcm_lintc_write_4(sc, BCM_LINTC_PMU_ROUTING_SET_REG, mask);
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BCM_LINTC_UNLOCK(sc);
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}
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static void
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bcm_lintc_mask(struct bcm_lintc_softc *sc, struct bcm_lintc_irqsrc *bli)
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{
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switch (bli->bli_irq) {
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case BCM_LINTC_TIMER0_IRQ:
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case BCM_LINTC_TIMER1_IRQ:
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case BCM_LINTC_TIMER2_IRQ:
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case BCM_LINTC_TIMER3_IRQ:
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bcm_lintc_timer_mask(sc, bli);
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return;
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case BCM_LINTC_MBOX0_IRQ:
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case BCM_LINTC_MBOX1_IRQ:
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case BCM_LINTC_MBOX2_IRQ:
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case BCM_LINTC_MBOX3_IRQ:
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return;
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case BCM_LINTC_GPU_IRQ:
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bcm_lintc_gpu_mask(sc, bli);
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return;
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case BCM_LINTC_PMU_IRQ:
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bcm_lintc_pmu_mask(sc, bli);
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return;
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default:
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panic("%s: not implemented for irq %u", __func__, bli->bli_irq);
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}
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}
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static void
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bcm_lintc_unmask(struct bcm_lintc_softc *sc, struct bcm_lintc_irqsrc *bli)
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{
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switch (bli->bli_irq) {
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case BCM_LINTC_TIMER0_IRQ:
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case BCM_LINTC_TIMER1_IRQ:
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case BCM_LINTC_TIMER2_IRQ:
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case BCM_LINTC_TIMER3_IRQ:
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bcm_lintc_timer_unmask(sc, bli);
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return;
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case BCM_LINTC_MBOX0_IRQ:
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case BCM_LINTC_MBOX1_IRQ:
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case BCM_LINTC_MBOX2_IRQ:
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case BCM_LINTC_MBOX3_IRQ:
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return;
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case BCM_LINTC_GPU_IRQ:
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bcm_lintc_gpu_unmask(sc, bli);
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return;
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case BCM_LINTC_PMU_IRQ:
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bcm_lintc_pmu_unmask(sc, bli);
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return;
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default:
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panic("%s: not implemented for irq %u", __func__, bli->bli_irq);
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}
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}
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#ifdef SMP
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static inline void
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bcm_lintc_ipi_write(struct bcm_lintc_softc *sc, cpuset_t cpus, u_int ipi)
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{
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u_int cpu;
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uint32_t mask;
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mask = 1 << ipi;
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for (cpu = 0; cpu < mp_ncpus; cpu++)
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if (CPU_ISSET(cpu, &cpus))
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bcm_lintc_write_4(sc, BCM_LINTC_MBOX0_SET_REG(cpu),
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mask);
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}
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static inline void
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bcm_lintc_ipi_dispatch(struct bcm_lintc_softc *sc, u_int cpu,
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struct trapframe *tf)
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{
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u_int ipi;
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uint32_t mask;
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mask = bcm_lintc_read_4(sc, BCM_LINTC_MBOX0_CLR_REG(cpu));
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if (mask == 0) {
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device_printf(sc->bls_dev, "Spurious ipi detected\n");
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return;
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}
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for (ipi = 0; mask != 0; mask >>= 1, ipi++) {
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if ((mask & 0x01) == 0)
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continue;
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/*
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* Clear an IPI before dispatching to not miss anyone
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* and make sure that it's observed by everybody.
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*/
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bcm_lintc_write_4(sc, BCM_LINTC_MBOX0_CLR_REG(cpu), 1 << ipi);
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dsb();
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intr_ipi_dispatch(ipi, tf);
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}
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}
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#endif
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static inline void
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bcm_lintc_irq_dispatch(struct bcm_lintc_softc *sc, u_int irq,
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struct trapframe *tf)
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{
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struct bcm_lintc_irqsrc *bli;
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bli = &sc->bls_isrcs[irq];
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if (intr_isrc_dispatch(&bli->bli_isrc, tf) != 0)
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device_printf(sc->bls_dev, "Stray irq %u detected\n", irq);
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}
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static int
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bcm_lintc_intr(void *arg)
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{
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struct bcm_lintc_softc *sc;
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u_int cpu;
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uint32_t num, reg;
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struct trapframe *tf;
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sc = arg;
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cpu = PCPU_GET(cpuid);
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tf = curthread->td_intr_frame;
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for (num = 0; ; num++) {
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reg = bcm_lintc_read_4(sc, BCM_LINTC_PENDING_REG(cpu));
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if ((reg & BCM_LINTC_PENDING_MASK) == 0)
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break;
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#ifdef SMP
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if (reg & BCM_LINTC_MBOX0_IRQ_MASK)
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bcm_lintc_ipi_dispatch(sc, cpu, tf);
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#endif
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if (reg & BCM_LINTC_TIMER0_IRQ_MASK)
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bcm_lintc_irq_dispatch(sc, BCM_LINTC_TIMER0_IRQ, tf);
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if (reg & BCM_LINTC_TIMER1_IRQ_MASK)
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bcm_lintc_irq_dispatch(sc, BCM_LINTC_TIMER1_IRQ, tf);
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if (reg & BCM_LINTC_TIMER2_IRQ_MASK)
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bcm_lintc_irq_dispatch(sc, BCM_LINTC_TIMER2_IRQ, tf);
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if (reg & BCM_LINTC_TIMER3_IRQ_MASK)
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bcm_lintc_irq_dispatch(sc, BCM_LINTC_TIMER3_IRQ, tf);
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if (reg & BCM_LINTC_GPU_IRQ_MASK)
|
|
bcm_lintc_irq_dispatch(sc, BCM_LINTC_GPU_IRQ, tf);
|
|
if (reg & BCM_LINTC_PMU_IRQ_MASK)
|
|
bcm_lintc_irq_dispatch(sc, BCM_LINTC_PMU_IRQ, tf);
|
|
|
|
arm_irq_memory_barrier(0); /* XXX */
|
|
}
|
|
reg &= ~BCM_LINTC_PENDING_MASK;
|
|
if (reg != 0)
|
|
device_printf(sc->bls_dev, "Unknown interrupt(s) %x\n", reg);
|
|
else if (num == 0)
|
|
device_printf(sc->bls_dev, "Spurious interrupt detected\n");
|
|
|
|
return (FILTER_HANDLED);
|
|
}
|
|
|
|
static void
|
|
bcm_lintc_disable_intr(device_t dev, struct intr_irqsrc *isrc)
|
|
{
|
|
|
|
bcm_lintc_mask(device_get_softc(dev), (struct bcm_lintc_irqsrc *)isrc);
|
|
}
|
|
|
|
static void
|
|
bcm_lintc_enable_intr(device_t dev, struct intr_irqsrc *isrc)
|
|
{
|
|
struct bcm_lintc_irqsrc *bli = (struct bcm_lintc_irqsrc *)isrc;
|
|
|
|
arm_irq_memory_barrier(bli->bli_irq);
|
|
bcm_lintc_unmask(device_get_softc(dev), bli);
|
|
}
|
|
|
|
static int
|
|
bcm_lintc_map_intr(device_t dev, struct intr_map_data *data,
|
|
struct intr_irqsrc **isrcp)
|
|
{
|
|
struct intr_map_data_fdt *daf;
|
|
struct bcm_lintc_softc *sc;
|
|
|
|
if (data->type != INTR_MAP_DATA_FDT)
|
|
return (ENOTSUP);
|
|
|
|
daf = (struct intr_map_data_fdt *)data;
|
|
if (daf->ncells != 1 || daf->cells[0] >= BCM_LINTC_NIRQS)
|
|
return (EINVAL);
|
|
|
|
sc = device_get_softc(dev);
|
|
*isrcp = &sc->bls_isrcs[daf->cells[0]].bli_isrc;
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
bcm_lintc_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
|
|
{
|
|
struct bcm_lintc_irqsrc *bli = (struct bcm_lintc_irqsrc *)isrc;
|
|
|
|
if (bli->bli_irq == BCM_LINTC_GPU_IRQ)
|
|
bcm_lintc_gpu_mask(device_get_softc(dev), bli);
|
|
else {
|
|
/*
|
|
* Handler for PPI interrupt does not make sense much unless
|
|
* there is one bound ithread for each core for it. Thus the
|
|
* interrupt can be masked on current core only while ithread
|
|
* bounded to this core ensures unmasking on the same core.
|
|
*/
|
|
panic ("%s: handlers are not supported", __func__);
|
|
}
|
|
}
|
|
|
|
static void
|
|
bcm_lintc_post_ithread(device_t dev, struct intr_irqsrc *isrc)
|
|
{
|
|
struct bcm_lintc_irqsrc *bli = (struct bcm_lintc_irqsrc *)isrc;
|
|
|
|
if (bli->bli_irq == BCM_LINTC_GPU_IRQ)
|
|
bcm_lintc_gpu_unmask(device_get_softc(dev), bli);
|
|
else {
|
|
/* See comment in bcm_lintc_pre_ithread(). */
|
|
panic ("%s: handlers are not supported", __func__);
|
|
}
|
|
}
|
|
|
|
static void
|
|
bcm_lintc_post_filter(device_t dev, struct intr_irqsrc *isrc)
|
|
{
|
|
}
|
|
|
|
static int
|
|
bcm_lintc_setup_intr(device_t dev, struct intr_irqsrc *isrc,
|
|
struct resource *res, struct intr_map_data *data)
|
|
{
|
|
struct bcm_lintc_softc *sc;
|
|
|
|
if (isrc->isrc_handlers == 0 && isrc->isrc_flags & INTR_ISRCF_PPI) {
|
|
sc = device_get_softc(dev);
|
|
BCM_LINTC_LOCK(sc);
|
|
CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
|
|
BCM_LINTC_UNLOCK(sc);
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
#ifdef SMP
|
|
static void
|
|
bcm_lintc_init_rwreg_on_ap(struct bcm_lintc_softc *sc, u_int cpu, u_int irq,
|
|
uint32_t reg, uint32_t mask)
|
|
{
|
|
|
|
if (intr_isrc_init_on_cpu(&sc->bls_isrcs[irq].bli_isrc, cpu))
|
|
bcm_lintc_rwreg_set(sc, reg, mask);
|
|
}
|
|
|
|
static void
|
|
bcm_lintc_init_pmu_on_ap(struct bcm_lintc_softc *sc, u_int cpu)
|
|
{
|
|
struct intr_irqsrc *isrc = &sc->bls_isrcs[BCM_LINTC_PMU_IRQ].bli_isrc;
|
|
|
|
if (intr_isrc_init_on_cpu(isrc, cpu)) {
|
|
/* Write-set register. */
|
|
bcm_lintc_write_4(sc, BCM_LINTC_PMU_ROUTING_SET_REG,
|
|
BCM_LINTC_PIRR_IRQ_EN_CORE(cpu));
|
|
}
|
|
}
|
|
|
|
static void
|
|
bcm_lintc_init_secondary(device_t dev)
|
|
{
|
|
u_int cpu;
|
|
struct bcm_lintc_softc *sc;
|
|
|
|
cpu = PCPU_GET(cpuid);
|
|
sc = device_get_softc(dev);
|
|
|
|
BCM_LINTC_LOCK(sc);
|
|
bcm_lintc_init_rwreg_on_ap(sc, cpu, BCM_LINTC_TIMER0_IRQ,
|
|
BCM_LINTC_TIMER_CFG_REG(cpu), BCM_LINTC_TCR_IRQ_EN_TIMER(0));
|
|
bcm_lintc_init_rwreg_on_ap(sc, cpu, BCM_LINTC_TIMER1_IRQ,
|
|
BCM_LINTC_TIMER_CFG_REG(cpu), BCM_LINTC_TCR_IRQ_EN_TIMER(1));
|
|
bcm_lintc_init_rwreg_on_ap(sc, cpu, BCM_LINTC_TIMER2_IRQ,
|
|
BCM_LINTC_TIMER_CFG_REG(cpu), BCM_LINTC_TCR_IRQ_EN_TIMER(2));
|
|
bcm_lintc_init_rwreg_on_ap(sc, cpu, BCM_LINTC_TIMER3_IRQ,
|
|
BCM_LINTC_TIMER_CFG_REG(cpu), BCM_LINTC_TCR_IRQ_EN_TIMER(3));
|
|
bcm_lintc_init_pmu_on_ap(sc, cpu);
|
|
BCM_LINTC_UNLOCK(sc);
|
|
}
|
|
|
|
static void
|
|
bcm_lintc_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus,
|
|
u_int ipi)
|
|
{
|
|
struct bcm_lintc_softc *sc = device_get_softc(dev);
|
|
|
|
KASSERT(isrc == &sc->bls_isrcs[BCM_LINTC_MBOX0_IRQ].bli_isrc,
|
|
("%s: bad ISRC %p argument", __func__, isrc));
|
|
bcm_lintc_ipi_write(sc, cpus, ipi);
|
|
}
|
|
|
|
static int
|
|
bcm_lintc_ipi_setup(device_t dev, u_int ipi, struct intr_irqsrc **isrcp)
|
|
{
|
|
struct bcm_lintc_softc *sc = device_get_softc(dev);
|
|
|
|
KASSERT(ipi < BCM_LINTC_NIPIS, ("%s: too high ipi %u", __func__, ipi));
|
|
|
|
*isrcp = &sc->bls_isrcs[BCM_LINTC_MBOX0_IRQ].bli_isrc;
|
|
return (0);
|
|
}
|
|
#endif
|
|
|
|
static int
|
|
bcm_lintc_pic_attach(struct bcm_lintc_softc *sc)
|
|
{
|
|
struct bcm_lintc_irqsrc *bisrcs;
|
|
struct intr_pic *pic;
|
|
int error;
|
|
u_int flags;
|
|
uint32_t irq;
|
|
const char *name;
|
|
intptr_t xref;
|
|
|
|
bisrcs = sc->bls_isrcs;
|
|
name = device_get_nameunit(sc->bls_dev);
|
|
for (irq = 0; irq < BCM_LINTC_NIRQS; irq++) {
|
|
bisrcs[irq].bli_irq = irq;
|
|
switch (irq) {
|
|
case BCM_LINTC_TIMER0_IRQ:
|
|
bisrcs[irq].bli_mask = BCM_LINTC_TCR_IRQ_EN_TIMER(0);
|
|
flags = INTR_ISRCF_PPI;
|
|
break;
|
|
case BCM_LINTC_TIMER1_IRQ:
|
|
bisrcs[irq].bli_mask = BCM_LINTC_TCR_IRQ_EN_TIMER(1);
|
|
flags = INTR_ISRCF_PPI;
|
|
break;
|
|
case BCM_LINTC_TIMER2_IRQ:
|
|
bisrcs[irq].bli_mask = BCM_LINTC_TCR_IRQ_EN_TIMER(2);
|
|
flags = INTR_ISRCF_PPI;
|
|
break;
|
|
case BCM_LINTC_TIMER3_IRQ:
|
|
bisrcs[irq].bli_mask = BCM_LINTC_TCR_IRQ_EN_TIMER(3);
|
|
flags = INTR_ISRCF_PPI;
|
|
break;
|
|
case BCM_LINTC_MBOX0_IRQ:
|
|
case BCM_LINTC_MBOX1_IRQ:
|
|
case BCM_LINTC_MBOX2_IRQ:
|
|
case BCM_LINTC_MBOX3_IRQ:
|
|
bisrcs[irq].bli_value = 0; /* not used */
|
|
flags = INTR_ISRCF_IPI;
|
|
break;
|
|
case BCM_LINTC_GPU_IRQ:
|
|
bisrcs[irq].bli_value = BCM_LINTC_GIRR_IRQ_CORE(0);
|
|
flags = 0;
|
|
break;
|
|
case BCM_LINTC_PMU_IRQ:
|
|
bisrcs[irq].bli_value = 0; /* not used */
|
|
flags = INTR_ISRCF_PPI;
|
|
break;
|
|
default:
|
|
bisrcs[irq].bli_value = 0; /* not used */
|
|
flags = 0;
|
|
break;
|
|
}
|
|
|
|
error = intr_isrc_register(&bisrcs[irq].bli_isrc, sc->bls_dev,
|
|
flags, "%s,%u", name, irq);
|
|
if (error != 0)
|
|
return (error);
|
|
}
|
|
|
|
xref = OF_xref_from_node(ofw_bus_get_node(sc->bls_dev));
|
|
pic = intr_pic_register(sc->bls_dev, xref);
|
|
if (pic == NULL)
|
|
return (ENXIO);
|
|
|
|
return (intr_pic_claim_root(sc->bls_dev, xref, bcm_lintc_intr, sc, 0));
|
|
}
|
|
|
|
static int
|
|
bcm_lintc_probe(device_t dev)
|
|
{
|
|
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
|
|
if (!ofw_bus_is_compatible(dev, "brcm,bcm2836-l1-intc"))
|
|
return (ENXIO);
|
|
device_set_desc(dev, "BCM2836 Interrupt Controller");
|
|
return (BUS_PROBE_DEFAULT);
|
|
}
|
|
|
|
static int
|
|
bcm_lintc_attach(device_t dev)
|
|
{
|
|
struct bcm_lintc_softc *sc;
|
|
int cpu, rid;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
sc->bls_dev = dev;
|
|
if (bcm_lintc_sc != NULL)
|
|
return (ENXIO);
|
|
|
|
rid = 0;
|
|
sc->bls_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
|
|
RF_ACTIVE);
|
|
if (sc->bls_mem == NULL) {
|
|
device_printf(dev, "could not allocate memory resource\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
sc->bls_bst = rman_get_bustag(sc->bls_mem);
|
|
sc->bls_bsh = rman_get_bushandle(sc->bls_mem);
|
|
|
|
bcm_lintc_write_4(sc, BCM_LINTC_CONTROL_REG, 0);
|
|
bcm_lintc_write_4(sc, BCM_LINTC_PRESCALER_REG, BCM_LINTC_PSR_19_2);
|
|
|
|
/* Disable all timers on all cores. */
|
|
for (cpu = 0; cpu < 4; cpu++)
|
|
bcm_lintc_write_4(sc, BCM_LINTC_TIMER_CFG_REG(cpu), 0);
|
|
|
|
#ifdef SMP
|
|
/* Enable mailbox 0 on all cores used for IPI. */
|
|
for (cpu = 0; cpu < 4; cpu++)
|
|
bcm_lintc_write_4(sc, BCM_LINTC_MBOX_CFG_REG(cpu),
|
|
BCM_LINTC_MCR_IRQ_EN_MBOX(0));
|
|
#endif
|
|
|
|
if (bcm_lintc_pic_attach(sc) != 0) {
|
|
device_printf(dev, "could not attach PIC\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
BCM_LINTC_LOCK_INIT(sc);
|
|
bcm_lintc_sc = sc;
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t bcm_lintc_methods[] = {
|
|
DEVMETHOD(device_probe, bcm_lintc_probe),
|
|
DEVMETHOD(device_attach, bcm_lintc_attach),
|
|
|
|
DEVMETHOD(pic_disable_intr, bcm_lintc_disable_intr),
|
|
DEVMETHOD(pic_enable_intr, bcm_lintc_enable_intr),
|
|
DEVMETHOD(pic_map_intr, bcm_lintc_map_intr),
|
|
DEVMETHOD(pic_post_filter, bcm_lintc_post_filter),
|
|
DEVMETHOD(pic_post_ithread, bcm_lintc_post_ithread),
|
|
DEVMETHOD(pic_pre_ithread, bcm_lintc_pre_ithread),
|
|
DEVMETHOD(pic_setup_intr, bcm_lintc_setup_intr),
|
|
#ifdef SMP
|
|
DEVMETHOD(pic_init_secondary, bcm_lintc_init_secondary),
|
|
DEVMETHOD(pic_ipi_send, bcm_lintc_ipi_send),
|
|
DEVMETHOD(pic_ipi_setup, bcm_lintc_ipi_setup),
|
|
#endif
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t bcm_lintc_driver = {
|
|
"local_intc",
|
|
bcm_lintc_methods,
|
|
sizeof(struct bcm_lintc_softc),
|
|
};
|
|
|
|
static devclass_t bcm_lintc_devclass;
|
|
|
|
EARLY_DRIVER_MODULE(local_intc, simplebus, bcm_lintc_driver, bcm_lintc_devclass,
|
|
0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
|
|
#else
|
|
/*
|
|
* A driver for features of the bcm2836.
|
|
*/
|
|
|
|
struct bcm2836_softc {
|
|
device_t sc_dev;
|
|
struct resource *sc_mem;
|
|
};
|
|
|
|
static device_identify_t bcm2836_identify;
|
|
static device_probe_t bcm2836_probe;
|
|
static device_attach_t bcm2836_attach;
|
|
|
|
struct bcm2836_softc *softc;
|
|
|
|
static void
|
|
bcm2836_identify(driver_t *driver, device_t parent)
|
|
{
|
|
|
|
if (BUS_ADD_CHILD(parent, 0, "bcm2836", -1) == NULL)
|
|
device_printf(parent, "add child failed\n");
|
|
}
|
|
|
|
static int
|
|
bcm2836_probe(device_t dev)
|
|
{
|
|
|
|
if (softc != NULL)
|
|
return (ENXIO);
|
|
|
|
device_set_desc(dev, "Broadcom bcm2836");
|
|
|
|
return (BUS_PROBE_DEFAULT);
|
|
}
|
|
|
|
static int
|
|
bcm2836_attach(device_t dev)
|
|
{
|
|
int i, rid;
|
|
|
|
softc = device_get_softc(dev);
|
|
softc->sc_dev = dev;
|
|
|
|
rid = 0;
|
|
softc->sc_mem = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
|
|
ARM_LOCAL_BASE, ARM_LOCAL_BASE + ARM_LOCAL_SIZE, ARM_LOCAL_SIZE,
|
|
RF_ACTIVE);
|
|
if (softc->sc_mem == NULL) {
|
|
device_printf(dev, "could not allocate memory resource\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
bus_write_4(softc->sc_mem, ARM_LOCAL_CONTROL, 0);
|
|
bus_write_4(softc->sc_mem, ARM_LOCAL_PRESCALER, PRESCALER_19_2);
|
|
|
|
for (i = 0; i < 4; i++)
|
|
bus_write_4(softc->sc_mem, ARM_LOCAL_INT_TIMER(i), 0);
|
|
|
|
for (i = 0; i < 4; i++)
|
|
bus_write_4(softc->sc_mem, ARM_LOCAL_INT_MAILBOX(i), 1);
|
|
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
bcm2836_get_next_irq(int last_irq)
|
|
{
|
|
uint32_t reg;
|
|
int cpu;
|
|
int irq;
|
|
|
|
cpu = PCPU_GET(cpuid);
|
|
|
|
reg = bus_read_4(softc->sc_mem, ARM_LOCAL_INT_PENDING(cpu));
|
|
reg &= INT_PENDING_MASK;
|
|
if (reg == 0)
|
|
return (-1);
|
|
|
|
irq = ffs(reg) - 1;
|
|
|
|
return (irq);
|
|
}
|
|
|
|
void
|
|
bcm2836_mask_irq(uintptr_t irq)
|
|
{
|
|
uint32_t reg;
|
|
#ifdef SMP
|
|
int cpu;
|
|
#endif
|
|
int i;
|
|
|
|
if (irq < MAILBOX0_IRQ) {
|
|
for (i = 0; i < 4; i++) {
|
|
reg = bus_read_4(softc->sc_mem,
|
|
ARM_LOCAL_INT_TIMER(i));
|
|
reg &= ~(1 << irq);
|
|
bus_write_4(softc->sc_mem,
|
|
ARM_LOCAL_INT_TIMER(i), reg);
|
|
}
|
|
#ifdef SMP
|
|
} else if (irq == MAILBOX0_IRQ) {
|
|
/* Mailbox 0 for IPI */
|
|
cpu = PCPU_GET(cpuid);
|
|
reg = bus_read_4(softc->sc_mem, ARM_LOCAL_INT_MAILBOX(cpu));
|
|
reg &= ~MAILBOX0_IRQEN;
|
|
bus_write_4(softc->sc_mem, ARM_LOCAL_INT_MAILBOX(cpu), reg);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
void
|
|
bcm2836_unmask_irq(uintptr_t irq)
|
|
{
|
|
uint32_t reg;
|
|
#ifdef SMP
|
|
int cpu;
|
|
#endif
|
|
int i;
|
|
|
|
if (irq < MAILBOX0_IRQ) {
|
|
for (i = 0; i < 4; i++) {
|
|
reg = bus_read_4(softc->sc_mem,
|
|
ARM_LOCAL_INT_TIMER(i));
|
|
reg |= (1 << irq);
|
|
bus_write_4(softc->sc_mem,
|
|
ARM_LOCAL_INT_TIMER(i), reg);
|
|
}
|
|
#ifdef SMP
|
|
} else if (irq == MAILBOX0_IRQ) {
|
|
/* Mailbox 0 for IPI */
|
|
cpu = PCPU_GET(cpuid);
|
|
reg = bus_read_4(softc->sc_mem, ARM_LOCAL_INT_MAILBOX(cpu));
|
|
reg |= MAILBOX0_IRQEN;
|
|
bus_write_4(softc->sc_mem, ARM_LOCAL_INT_MAILBOX(cpu), reg);
|
|
#endif
|
|
}
|
|
}
|
|
|
|
static device_method_t bcm2836_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_identify, bcm2836_identify),
|
|
DEVMETHOD(device_probe, bcm2836_probe),
|
|
DEVMETHOD(device_attach, bcm2836_attach),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static devclass_t bcm2836_devclass;
|
|
|
|
static driver_t bcm2836_driver = {
|
|
"bcm2836",
|
|
bcm2836_methods,
|
|
sizeof(struct bcm2836_softc),
|
|
};
|
|
|
|
EARLY_DRIVER_MODULE(bcm2836, nexus, bcm2836_driver, bcm2836_devclass, 0, 0,
|
|
BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
|
|
#endif
|