434 lines
13 KiB
C
434 lines
13 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Inc. nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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#include "cvmx.h"
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#include "cvmx-sysinfo.h"
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#include "cvmx-compactflash.h"
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#ifndef MAX
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#define MAX(a,b) (((a)>(b))?(a):(b))
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#endif
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#define FLASH_RoundUP(_Dividend, _Divisor) (((_Dividend)+(_Divisor-1))/(_Divisor))
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/**
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* Convert nanosecond based time to setting used in the
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* boot bus timing register, based on timing multiple
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*
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*
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*/
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static uint32_t ns_to_tim_reg(int tim_mult, uint32_t nsecs)
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{
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uint32_t val;
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/* Compute # of eclock periods to get desired duration in nanoseconds */
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val = FLASH_RoundUP(nsecs * (cvmx_clock_get_rate(CVMX_CLOCK_SCLK)/1000000), 1000);
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/* Factor in timing multiple, if not 1 */
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if (tim_mult != 1)
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val = FLASH_RoundUP(val, tim_mult);
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return (val);
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}
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uint64_t cvmx_compactflash_generate_dma_tim(int tim_mult, uint16_t *ident_data, int *mwdma_mode_ptr)
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{
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cvmx_mio_boot_dma_timx_t dma_tim;
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int oe_a;
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int oe_n;
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int dma_acks;
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int dma_ackh;
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int dma_arq;
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int pause;
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int To,Tkr,Td;
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int mwdma_mode = -1;
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uint16_t word53_field_valid;
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uint16_t word63_mwdma;
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uint16_t word163_adv_timing_info;
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if (!ident_data)
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return 0;
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word53_field_valid = ident_data[53];
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word63_mwdma = ident_data[63];
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word163_adv_timing_info = ident_data[163];
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dma_tim.u64 = 0;
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/* Check for basic MWDMA modes */
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if (word53_field_valid & 0x2)
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{
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if (word63_mwdma & 0x4)
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mwdma_mode = 2;
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else if (word63_mwdma & 0x2)
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mwdma_mode = 1;
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else if (word63_mwdma & 0x1)
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mwdma_mode = 0;
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}
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/* Check for advanced MWDMA modes */
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switch ((word163_adv_timing_info >> 3) & 0x7)
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{
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case 1:
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mwdma_mode = 3;
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break;
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case 2:
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mwdma_mode = 4;
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break;
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default:
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break;
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}
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/* DMA is not supported by this card */
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if (mwdma_mode < 0)
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return 0;
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/* Now set up the DMA timing */
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switch (tim_mult)
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{
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case 1:
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dma_tim.s.tim_mult = 1;
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break;
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case 2:
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dma_tim.s.tim_mult = 2;
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break;
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case 4:
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dma_tim.s.tim_mult = 0;
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break;
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case 8:
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dma_tim.s.tim_mult = 3;
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break;
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default:
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cvmx_dprintf("ERROR: invalid boot bus dma tim_mult setting\n");
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break;
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}
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switch (mwdma_mode)
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{
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case 4:
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To = 80;
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Td = 55;
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Tkr = 20;
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oe_a = Td + 20; // Td (Seem to need more margin here....
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oe_n = MAX(To - oe_a, Tkr); // Tkr from cf spec, lengthened to meet To
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// oe_n + oe_h must be >= To (cycle time)
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dma_acks = 0; //Ti
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dma_ackh = 5; // Tj
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dma_arq = 8; // not spec'ed, value in eclocks, not affected by tim_mult
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pause = 25 - dma_arq * 1000/(cvmx_clock_get_rate(CVMX_CLOCK_SCLK)/1000000); // Tz
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break;
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case 3:
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To = 100;
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Td = 65;
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Tkr = 20;
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oe_a = Td + 20; // Td (Seem to need more margin here....
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oe_n = MAX(To - oe_a, Tkr); // Tkr from cf spec, lengthened to meet To
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// oe_n + oe_h must be >= To (cycle time)
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dma_acks = 0; //Ti
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dma_ackh = 5; // Tj
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dma_arq = 8; // not spec'ed, value in eclocks, not affected by tim_mult
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pause = 25 - dma_arq * 1000/(cvmx_clock_get_rate(CVMX_CLOCK_SCLK)/1000000); // Tz
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break;
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case 2:
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// +20 works
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// +10 works
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// + 10 + 0 fails
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// n=40, a=80 works
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To = 120;
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Td = 70;
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Tkr = 25;
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// oe_a 0 fudge doesn't work; 10 seems to
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oe_a = Td + 20 + 10; // Td (Seem to need more margin here....
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oe_n = MAX(To - oe_a, Tkr) + 10; // Tkr from cf spec, lengthened to meet To
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// oe_n 0 fudge fails;;; 10 boots
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// 20 ns fudge needed on dma_acks
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// oe_n + oe_h must be >= To (cycle time)
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dma_acks = 0 + 20; //Ti
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dma_ackh = 5; // Tj
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dma_arq = 8; // not spec'ed, value in eclocks, not affected by tim_mult
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pause = 25 - dma_arq * 1000/(cvmx_clock_get_rate(CVMX_CLOCK_SCLK)/1000000); // Tz
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// no fudge needed on pause
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break;
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case 1:
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case 0:
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default:
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cvmx_dprintf("ERROR: Unsupported DMA mode: %d\n", mwdma_mode);
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return(-1);
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break;
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}
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if (mwdma_mode_ptr)
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*mwdma_mode_ptr = mwdma_mode;
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dma_tim.s.dmack_pi = 1;
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dma_tim.s.oe_n = ns_to_tim_reg(tim_mult, oe_n);
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dma_tim.s.oe_a = ns_to_tim_reg(tim_mult, oe_a);
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dma_tim.s.dmack_s = ns_to_tim_reg(tim_mult, dma_acks);
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dma_tim.s.dmack_h = ns_to_tim_reg(tim_mult, dma_ackh);
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dma_tim.s.dmarq = dma_arq;
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dma_tim.s.pause = ns_to_tim_reg(tim_mult, pause);
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dma_tim.s.rd_dly = 0; /* Sample right on edge */
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/* writes only */
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dma_tim.s.we_n = ns_to_tim_reg(tim_mult, oe_n);
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dma_tim.s.we_a = ns_to_tim_reg(tim_mult, oe_a);
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#if 0
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cvmx_dprintf("ns to ticks (mult %d) of %d is: %d\n", TIM_MULT, 60, ns_to_tim_reg(60));
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cvmx_dprintf("oe_n: %d, oe_a: %d, dmack_s: %d, dmack_h: %d, dmarq: %d, pause: %d\n",
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dma_tim.s.oe_n, dma_tim.s.oe_a, dma_tim.s.dmack_s, dma_tim.s.dmack_h, dma_tim.s.dmarq, dma_tim.s.pause);
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#endif
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return(dma_tim.u64);
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}
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/**
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* Setup timing and region config to support a specific IDE PIO
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* mode over the bootbus.
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*
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* @param cs0 Bootbus region number connected to CS0 on the IDE device
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* @param cs1 Bootbus region number connected to CS1 on the IDE device
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* @param pio_mode PIO mode to set (0-6)
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*/
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void cvmx_compactflash_set_piomode(int cs0, int cs1, int pio_mode)
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{
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cvmx_mio_boot_reg_cfgx_t mio_boot_reg_cfg;
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cvmx_mio_boot_reg_timx_t mio_boot_reg_tim;
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int cs;
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int clocks_us; /* Number of clock cycles per microsec */
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int tim_mult;
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int use_iordy; /* Set for PIO0-4, not set for PIO5-6 */
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int t1; /* These t names are timing parameters from the ATA spec */
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int t2;
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int t2i;
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int t4;
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int t6;
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int t6z;
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int t9;
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/* PIO modes 0-4 all allow the device to deassert IORDY to slow down
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the host */
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use_iordy = 1;
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/* Use the PIO mode to determine timing parameters */
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switch(pio_mode) {
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case 6:
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/* CF spec say IORDY should be ignore in PIO 5 */
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use_iordy = 0;
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t1 = 10;
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t2 = 55;
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t2i = 20;
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t4 = 5;
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t6 = 5;
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t6z = 20;
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t9 = 10;
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break;
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case 5:
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/* CF spec say IORDY should be ignore in PIO 6 */
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use_iordy = 0;
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t1 = 15;
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t2 = 65;
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t2i = 25;
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t4 = 5;
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t6 = 5;
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t6z = 20;
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t9 = 10;
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break;
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case 4:
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t1 = 25;
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t2 = 70;
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t2i = 25;
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t4 = 10;
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t6 = 5;
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t6z = 30;
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t9 = 10;
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break;
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case 3:
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t1 = 30;
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t2 = 80;
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t2i = 70;
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t4 = 10;
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t6 = 5;
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t6z = 30;
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t9 = 10;
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break;
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case 2:
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t1 = 30;
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t2 = 100;
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t2i = 0;
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t4 = 15;
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t6 = 5;
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t6z = 30;
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t9 = 10;
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break;
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case 1:
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t1 = 50;
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t2 = 125;
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t2i = 0;
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t4 = 20;
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t6 = 5;
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t6z = 30;
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t9 = 15;
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break;
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default:
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t1 = 70;
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t2 = 165;
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t2i = 0;
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t4 = 30;
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t6 = 5;
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t6z = 30;
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t9 = 20;
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break;
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}
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/* Convert times in ns to clock cycles, rounding up */
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clocks_us = FLASH_RoundUP(cvmx_clock_get_rate(CVMX_CLOCK_SCLK), 1000000);
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/* Convert times in clock cycles, rounding up. Octeon parameters are in
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minus one notation, so take off one after the conversion */
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t1 = FLASH_RoundUP(t1 * clocks_us, 1000);
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if (t1)
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t1--;
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t2 = FLASH_RoundUP(t2 * clocks_us, 1000);
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if (t2)
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t2--;
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t2i = FLASH_RoundUP(t2i * clocks_us, 1000);
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if (t2i)
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t2i--;
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t4 = FLASH_RoundUP(t4 * clocks_us, 1000);
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if (t4)
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t4--;
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t6 = FLASH_RoundUP(t6 * clocks_us, 1000);
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if (t6)
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t6--;
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t6z = FLASH_RoundUP(t6z * clocks_us, 1000);
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if (t6z)
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t6z--;
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t9 = FLASH_RoundUP(t9 * clocks_us, 1000);
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if (t9)
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t9--;
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/* Start using a scale factor of one cycle. Keep doubling it until
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the parameters fit in their fields. Since t2 is the largest number,
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we only need to check it */
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tim_mult = 1;
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while (t2 >= 1<<6)
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{
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t1 = FLASH_RoundUP(t1, 2);
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t2 = FLASH_RoundUP(t2, 2);
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t2i = FLASH_RoundUP(t2i, 2);
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t4 = FLASH_RoundUP(t4, 2);
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t6 = FLASH_RoundUP(t6, 2);
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t6z = FLASH_RoundUP(t6z, 2);
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t9 = FLASH_RoundUP(t9, 2);
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tim_mult *= 2;
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}
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cs = cs0;
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do {
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mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs));
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mio_boot_reg_cfg.s.dmack = 0; /* Don't assert DMACK on access */
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switch(tim_mult) {
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case 1:
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mio_boot_reg_cfg.s.tim_mult = 1;
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break;
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case 2:
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mio_boot_reg_cfg.s.tim_mult = 2;
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break;
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case 4:
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mio_boot_reg_cfg.s.tim_mult = 0;
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break;
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case 8:
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default:
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mio_boot_reg_cfg.s.tim_mult = 3;
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break;
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}
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mio_boot_reg_cfg.s.rd_dly = 0; /* Sample on falling edge of BOOT_OE */
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mio_boot_reg_cfg.s.sam = 0; /* Don't combine write and output enable */
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mio_boot_reg_cfg.s.we_ext = 0; /* No write enable extension */
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mio_boot_reg_cfg.s.oe_ext = 0; /* No read enable extension */
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mio_boot_reg_cfg.s.en = 1; /* Enable this region */
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mio_boot_reg_cfg.s.orbit = 0; /* Don't combine with previos region */
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mio_boot_reg_cfg.s.width = 1; /* 16 bits wide */
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cvmx_write_csr(CVMX_MIO_BOOT_REG_CFGX(cs), mio_boot_reg_cfg.u64);
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if(cs == cs0)
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cs = cs1;
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else
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cs = cs0;
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} while(cs != cs0);
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mio_boot_reg_tim.u64 = 0;
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mio_boot_reg_tim.s.pagem = 0; /* Disable page mode */
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mio_boot_reg_tim.s.waitm = use_iordy; /* Enable dynamic timing */
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mio_boot_reg_tim.s.pages = 0; /* Pages are disabled */
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mio_boot_reg_tim.s.ale = 8; /* If someone uses ALE, this seems to work */
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mio_boot_reg_tim.s.page = 0; /* Not used */
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mio_boot_reg_tim.s.wait = 0; /* Time after IORDY to coninue to assert the data */
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mio_boot_reg_tim.s.pause = 0; /* Time after CE that signals stay valid */
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mio_boot_reg_tim.s.wr_hld = t9; /* How long to hold after a write */
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mio_boot_reg_tim.s.rd_hld = t9; /* How long to wait after a read for device to tristate */
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mio_boot_reg_tim.s.we = t2; /* How long write enable is asserted */
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mio_boot_reg_tim.s.oe = t2; /* How long read enable is asserted */
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mio_boot_reg_tim.s.ce = t1; /* Time after CE that read/write starts */
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mio_boot_reg_tim.s.adr = 1; /* Time before CE that address is valid */
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/* Program the bootbus region timing for both chip selects */
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cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cs0), mio_boot_reg_tim.u64);
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cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cs1), mio_boot_reg_tim.u64);
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}
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