314 lines
11 KiB
C
314 lines
11 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Inc. nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* @file
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*
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* Support library for the hardware work queue timers.
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*
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* <hr>$Revision: 70030 $<hr>
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*/
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#include "executive-config.h"
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#include "cvmx-config.h"
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#include "cvmx.h"
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#include "cvmx-sysinfo.h"
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#include "cvmx-tim.h"
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#include "cvmx-bootmem.h"
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/* CSR typedefs have been moved to cvmx-tim-defs.h */
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/**
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* Global structure holding the state of all timers.
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*/
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CVMX_SHARED cvmx_tim_t cvmx_tim;
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#ifdef CVMX_ENABLE_TIMER_FUNCTIONS
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/**
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* Setup a timer for use. Must be called before the timer
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* can be used.
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*
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* @param tick Time between each bucket in microseconds. This must not be
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* smaller than 1024/(clock frequency in MHz).
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* @param max_ticks The maximum number of ticks the timer must be able
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* to schedule in the future. There are guaranteed to be enough
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* timer buckets such that:
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* number of buckets >= max_ticks.
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* @return Zero on success. Negative on error. Failures are possible
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* if the number of buckets needed is too large or memory
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* allocation fails for creating the buckets.
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*/
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int cvmx_tim_setup(uint64_t tick, uint64_t max_ticks)
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{
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uint64_t timer_id;
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int error = -1;
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uint64_t tim_clock_hz = cvmx_clock_get_rate(CVMX_CLOCK_TIM);
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uint64_t hw_tick_ns;
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uint64_t hw_tick_ns_allowed;
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uint64_t tick_ns = 1000 * tick;
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int i;
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uint32_t temp;
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int timer_thr = 1024;
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/* for the simulator */
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if (tim_clock_hz == 0)
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tim_clock_hz = 800000000;
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if (OCTEON_IS_MODEL(OCTEON_CN68XX))
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{
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cvmx_tim_fr_rn_tt_t fr_tt;
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fr_tt.u64 = cvmx_read_csr(CVMX_TIM_FR_RN_TT);
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timer_thr = fr_tt.s.fr_rn_tt;
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}
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hw_tick_ns = timer_thr * 1000000000ull / tim_clock_hz;
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/*
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* Double the minimal allowed tick to 2 * HW tick. tick between
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* (hw_tick_ns, 2*hw_tick_ns) will set config_ring1.s.interval
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* to zero, or 1024 cycles. This is not enough time for the timer unit
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* to fetch the bucket data, Resulting in timer ring error interrupt
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* be always generated. Avoid such setting in software.
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*/
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hw_tick_ns_allowed = hw_tick_ns * 2;
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/* Make sure the timers are stopped */
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cvmx_tim_stop();
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/* Reinitialize out timer state */
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memset(&cvmx_tim, 0, sizeof(cvmx_tim));
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if (tick_ns < hw_tick_ns_allowed)
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{
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cvmx_dprintf("ERROR: cvmx_tim_setup: Requested tick %lu(ns) is smaller than"
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" the minimal ticks allowed by hardware %lu(ns)\n",
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tick_ns, hw_tick_ns_allowed);
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return error;
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}
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else if (tick_ns > 4194304 * hw_tick_ns)
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{
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cvmx_dprintf("ERROR: cvmx_tim_setup: Requested tick %lu(ns) is greater than"
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" the max ticks %lu(ns)\n", tick_ns, hw_tick_ns);
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return error;
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}
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for (i=2; i<20; i++)
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{
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if (tick_ns < (hw_tick_ns << i))
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break;
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}
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cvmx_tim.max_ticks = (uint32_t)max_ticks;
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cvmx_tim.bucket_shift = (uint32_t)(i - 1 + 10);
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cvmx_tim.tick_cycles = tick * tim_clock_hz / 1000000;
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temp = (max_ticks * cvmx_tim.tick_cycles) >> cvmx_tim.bucket_shift;
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/* round up to nearest power of 2 */
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temp -= 1;
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temp = temp | (temp >> 1);
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temp = temp | (temp >> 2);
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temp = temp | (temp >> 4);
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temp = temp | (temp >> 8);
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temp = temp | (temp >> 16);
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cvmx_tim.num_buckets = temp + 1;
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/* ensure input params fall into permitted ranges */
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if ((cvmx_tim.num_buckets < 3) || cvmx_tim.num_buckets > 1048576)
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{
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cvmx_dprintf("ERROR: cvmx_tim_setup: num_buckets out of range\n");
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return error;
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}
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/* Allocate the timer buckets from hardware addressable memory */
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cvmx_tim.bucket = cvmx_bootmem_alloc(CVMX_TIM_NUM_TIMERS * cvmx_tim.num_buckets
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* sizeof(cvmx_tim_bucket_entry_t), CVMX_CACHE_LINE_SIZE);
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if (cvmx_tim.bucket == NULL)
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{
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cvmx_dprintf("ERROR: cvmx_tim_setup: allocation problem\n");
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return error;
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}
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memset(cvmx_tim.bucket, 0, CVMX_TIM_NUM_TIMERS * cvmx_tim.num_buckets * sizeof(cvmx_tim_bucket_entry_t));
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cvmx_tim.start_time = 0;
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/* Loop through all timers */
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for (timer_id = 0; timer_id<CVMX_TIM_NUM_TIMERS; timer_id++)
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{
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int interval = ((1 << (cvmx_tim.bucket_shift - 10)) - 1);
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cvmx_tim_bucket_entry_t *bucket = cvmx_tim.bucket + timer_id * cvmx_tim.num_buckets;
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if (OCTEON_IS_MODEL(OCTEON_CN68XX))
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{
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cvmx_tim_ringx_ctl0_t ring_ctl0;
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cvmx_tim_ringx_ctl1_t ring_ctl1;
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cvmx_tim_ringx_ctl2_t ring_ctl2;
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cvmx_tim_reg_flags_t reg_flags;
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/* Tell the hardware where about the bucket array */
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ring_ctl2.u64 = 0;
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ring_ctl2.s.csize = CVMX_FPA_TIMER_POOL_SIZE / 8;
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ring_ctl2.s.base = cvmx_ptr_to_phys(bucket) >> 5;
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cvmx_write_csr(CVMX_TIM_RINGX_CTL2(timer_id), ring_ctl2.u64);
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reg_flags.u64 = cvmx_read_csr(CVMX_TIM_REG_FLAGS);
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ring_ctl1.u64 = 0;
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ring_ctl1.s.cpool = ((reg_flags.s.ena_dfb == 0) ? CVMX_FPA_TIMER_POOL : 0);
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ring_ctl1.s.bsize = cvmx_tim.num_buckets - 1;
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cvmx_write_csr(CVMX_TIM_RINGX_CTL1(timer_id), ring_ctl1.u64);
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ring_ctl0.u64 = 0;
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ring_ctl0.s.timercount = interval + timer_id * interval / CVMX_TIM_NUM_TIMERS;
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cvmx_write_csr(CVMX_TIM_RINGX_CTL0(timer_id), ring_ctl0.u64);
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ring_ctl0.u64 = cvmx_read_csr(CVMX_TIM_RINGX_CTL0(timer_id));
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ring_ctl0.s.ena = 1;
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ring_ctl0.s.interval = interval;
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cvmx_write_csr(CVMX_TIM_RINGX_CTL0(timer_id), ring_ctl0.u64);
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ring_ctl0.u64 = cvmx_read_csr(CVMX_TIM_RINGX_CTL0(timer_id));
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}
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else
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{
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cvmx_tim_mem_ring0_t config_ring0;
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cvmx_tim_mem_ring1_t config_ring1;
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/* Tell the hardware where about the bucket array */
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config_ring0.u64 = 0;
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config_ring0.s.first_bucket = cvmx_ptr_to_phys(bucket) >> 5;
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config_ring0.s.num_buckets = cvmx_tim.num_buckets - 1;
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config_ring0.s.ring = timer_id;
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cvmx_write_csr(CVMX_TIM_MEM_RING0, config_ring0.u64);
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/* Tell the hardware the size of each chunk block in pointers */
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config_ring1.u64 = 0;
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config_ring1.s.enable = 1;
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config_ring1.s.pool = CVMX_FPA_TIMER_POOL;
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config_ring1.s.words_per_chunk = CVMX_FPA_TIMER_POOL_SIZE / 8;
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config_ring1.s.interval = interval;
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config_ring1.s.ring = timer_id;
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cvmx_write_csr(CVMX_TIM_MEM_RING1, config_ring1.u64);
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}
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}
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return 0;
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}
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#endif
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/**
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* Start the hardware timer processing
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*/
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void cvmx_tim_start(void)
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{
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cvmx_tim_control_t control;
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control.u64 = cvmx_read_csr(CVMX_TIM_REG_FLAGS);
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control.s.enable_dwb = 1;
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control.s.enable_timers = 1;
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/* Remember when we started the timers */
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cvmx_tim.start_time = cvmx_clock_get_count(CVMX_CLOCK_TIM);
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cvmx_write_csr(CVMX_TIM_REG_FLAGS, control.u64);
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}
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/**
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* Stop the hardware timer processing. Timers stay configured.
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*/
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void cvmx_tim_stop(void)
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{
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cvmx_tim_control_t control;
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control.u64 = cvmx_read_csr(CVMX_TIM_REG_FLAGS);
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control.s.enable_dwb = 0;
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control.s.enable_timers = 0;
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cvmx_write_csr(CVMX_TIM_REG_FLAGS, control.u64);
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}
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/**
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* Stop the timer. After this the timer must be setup again
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* before use.
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*/
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#ifdef CVMX_ENABLE_TIMER_FUNCTIONS
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void cvmx_tim_shutdown(void)
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{
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uint32_t bucket;
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uint64_t timer_id;
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uint64_t entries_per_chunk;
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/* Make sure the timers are stopped */
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cvmx_tim_stop();
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entries_per_chunk = CVMX_FPA_TIMER_POOL_SIZE/8 - 1;
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/* Now walk all buckets freeing the chunks */
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for (timer_id = 0; timer_id<CVMX_TIM_NUM_TIMERS; timer_id++)
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{
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for (bucket=0; bucket<cvmx_tim.num_buckets; bucket++)
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{
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uint64_t chunk_addr;
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uint64_t next_chunk_addr;
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cvmx_tim_bucket_entry_t *bucket_ptr = cvmx_tim.bucket + timer_id * cvmx_tim.num_buckets + bucket;
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CVMX_PREFETCH128(CAST64(bucket_ptr)); /* prefetch the next cacheline for future buckets */
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/* Each bucket contains a list of chunks */
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chunk_addr = bucket_ptr->first_chunk_addr;
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while (bucket_ptr->num_entries)
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{
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#ifdef DEBUG
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cvmx_dprintf("Freeing Timer Chunk 0x%llx\n", CAST64(chunk_addr));
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#endif
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/* Read next chunk pointer from end of the current chunk */
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next_chunk_addr = cvmx_read_csr(CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, chunk_addr + CVMX_FPA_TIMER_POOL_SIZE - 8));
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cvmx_fpa_free(cvmx_phys_to_ptr(chunk_addr), CVMX_FPA_TIMER_POOL, 0);
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chunk_addr = next_chunk_addr;
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if (bucket_ptr->num_entries > entries_per_chunk)
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bucket_ptr->num_entries -= entries_per_chunk;
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else
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bucket_ptr->num_entries = 0;
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}
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}
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}
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}
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#endif
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