265 lines
8.9 KiB
C
265 lines
8.9 KiB
C
/*-
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*******************************************************************************
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Copyright (C) 2015 Annapurna Labs Ltd.
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This file may be licensed under the terms of the Annapurna Labs Commercial
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License Agreement.
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Alternatively, this file can be distributed under the terms of the GNU General
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Public License V2 as published by the Free Software Foundation and can be
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found at http://www.gnu.org/licenses/gpl-2.0.html
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Alternatively, redistribution and use in source and binary forms, with or
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without modification, are permitted provided that the following conditions are
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met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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/**
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* @{
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* @file al_hal_an_lt_wrapper_regs.h
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*
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* @brief ... registers
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*
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*/
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#ifndef __AL_HAL_AN_LT_wrapper_REGS_H__
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#define __AL_HAL_AN_LT_wrapper_REGS_H__
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#include "al_hal_plat_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Unit Registers
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*/
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struct al_an_lt_wrapper_gen {
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/* [0x0] AN LT wrapper Version */
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uint32_t version;
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/* [0x4] AN LT general configuration */
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uint32_t cfg;
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uint32_t rsrvd[14];
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};
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struct al_an_lt_wrapper_an_lt {
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/* [0x0] AN LT register file address */
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uint32_t addr;
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/* [0x4] PCS register file data */
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uint32_t data;
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/* [0x8] AN LT control signals */
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uint32_t ctrl;
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/* [0xc] AN LT status signals */
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uint32_t status;
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uint32_t rsrvd[4];
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};
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enum al_eth_an_lt_unit {
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AL_ETH_AN_LT_UNIT_32_BIT = 0,
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AL_ETH_AN_LT_UNIT_20_BIT = 1,
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AL_ETH_AN_LT_UNIT_16_BIT = 2,
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};
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struct al_an_lt_wrapper_regs {
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uint32_t rsrvd_0[64];
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struct al_an_lt_wrapper_gen gen; /* [0x100] */
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struct al_an_lt_wrapper_an_lt an_lt[3]; /* [0x140] */
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};
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/*
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* Registers Fields
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*/
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/**** version register ****/
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/* Revision number (Minor) */
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#define AN_LT_WRAPPER_GEN_VERSION_RELEASE_NUM_MINOR_MASK 0x000000FF
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#define AN_LT_WRAPPER_GEN_VERSION_RELEASE_NUM_MINOR_SHIFT 0
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/* Revision number (Major) */
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#define AN_LT_WRAPPER_GEN_VERSION_RELEASE_NUM_MAJOR_MASK 0x0000FF00
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#define AN_LT_WRAPPER_GEN_VERSION_RELEASE_NUM_MAJOR_SHIFT 8
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/* Date of release */
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#define AN_LT_WRAPPER_GEN_VERSION_DATE_DAY_MASK 0x001F0000
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#define AN_LT_WRAPPER_GEN_VERSION_DATE_DAY_SHIFT 16
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/* Month of release */
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#define AN_LT_WRAPPER_GEN_VERSION_DATA_MONTH_MASK 0x01E00000
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#define AN_LT_WRAPPER_GEN_VERSION_DATA_MONTH_SHIFT 21
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/* Year of release (starting from 2000) */
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#define AN_LT_WRAPPER_GEN_VERSION_DATE_YEAR_MASK 0x3E000000
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#define AN_LT_WRAPPER_GEN_VERSION_DATE_YEAR_SHIFT 25
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/* Reserved */
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#define AN_LT_WRAPPER_GEN_VERSION_RESERVED_MASK 0xC0000000
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#define AN_LT_WRAPPER_GEN_VERSION_RESERVED_SHIFT 30
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/**** cfg register ****/
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/*
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* selection between different bus widths:
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* 0 – 16
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* 1 – 20
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* 2 – 32
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* 3 – N/A
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*/
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#define AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_MASK 0x00000003
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#define AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_RX_SHIFT 0
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/*
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* selection between different bus widths:
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* 0 – 16
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* 1 – 20
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* 2 – 32
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* 3 – N/A
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*/
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#define AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_MASK 0x0000000C
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#define AN_LT_WRAPPER_GEN_CFG_AN_LT_SEL_TX_SHIFT 2
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/* bypass the AN/LT block */
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#define AN_LT_WRAPPER_GEN_CFG_BYPASS_RX (1 << 4)
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/* bypass the AN/LT block */
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#define AN_LT_WRAPPER_GEN_CFG_BYPASS_TX (1 << 5)
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/**** addr register ****/
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/* Address value */
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#define AN_LT_WRAPPER_AN_LT_ADDR_VAL_MASK 0x000007FF
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#define AN_LT_WRAPPER_AN_LT_ADDR_VAL_SHIFT 0
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/**** data register ****/
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/* Data value */
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#define AN_LT_WRAPPER_AN_LT_DATA_VAL_MASK 0x0000FFFF
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#define AN_LT_WRAPPER_AN_LT_DATA_VAL_SHIFT 0
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/**** ctrl register ****/
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/*
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* Default Auto-Negotiation Enable. If ‘1’, the auto-negotiation process will
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* start after reset de-assertion. The application can also start the
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* auto-negotiation process by writing the KXAN_CONTROL.an_enable bit with ‘1’.
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* Important: This signal is OR'ed with the KXAN_CONTROL.an_enable bit. Hence,
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* when asserted (1) the application is unable to disable autonegotiation and
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* writing the an_enable bit has no effect.
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* Note: Even if enabled by this pin, the application must write the correct
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* abilities in the KXAN_ABILITY_1/2/3 registers within 60ms from reset
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* deassertion (break_link_timer).
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*/
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#define AN_LT_WRAPPER_AN_LT_CTRL_AN_ENA (1 << 0)
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/*
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* If set to 1, the Arbitration State Machine reached the TRANSMIT_DISABLE
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* state.
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*/
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#define AN_LT_WRAPPER_AN_LT_CTRL_AN_DIS_TIMER (1 << 1)
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#define AN_LT_WRAPPER_AN_LT_CTRL_LINK_STATUS_KX (1 << 4)
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#define AN_LT_WRAPPER_AN_LT_CTRL_LINK_STATUS_KX4 (1 << 5)
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#define AN_LT_WRAPPER_AN_LT_CTRL_LINK_STATUS (1 << 6)
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/*
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* PHY LOS indication selection
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* 0 - Select input from the SerDes
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* 1 - Select register value from phy_los_in_def
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*/
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#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_IN_SEL (1 << 8)
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/* PHY LOS default value */
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#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_IN_DEF (1 << 9)
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/* PHY LOS polarity */
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#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_IN_POL (1 << 10)
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/*
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* PHY LOS indication selection
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* 0 – select AN output
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* 1 - Select register value from phy_los_out_def
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* 2 - Select input from the SerDes
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* 3 – 0
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*/
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#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_OUT_SEL_MASK 0x00003000
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#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_OUT_SEL_SHIFT 12
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/* PHY LOS default value */
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#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_OUT_DEF (1 << 14)
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/* PHY LOS polarity */
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#define AN_LT_WRAPPER_AN_LT_CTRL_PHY_LOS_OUT_POL (1 << 15)
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/**** status register ****/
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/* Auto-Negotiation Done. If ‘1’, the auto-negotiation process has completed. */
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#define AN_LT_WRAPPER_AN_LT_STATUS_AN_DONE (1 << 0)
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/*
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* If set to 1, auto-negotiation is enabled on the link. It represents the
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* enable control bit KXAN_CONTROL.an_enable. When set to 1, the signals
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* an_status/an_select are valid.
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*/
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#define AN_LT_WRAPPER_AN_LT_STATUS_AN_VAL (1 << 1)
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/*
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* If set to 0, auto-negotiation is in progress, if set to 1, the Arbitration
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* State Machine reached the AN_GOOD_CHECK state (i.e. before autonegotiation is
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* done, but the link no longer is used to transfer DME pages). Stays asserted
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* also during AN_GOOD (autoneg done).
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*/
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#define AN_LT_WRAPPER_AN_LT_STATUS_AN_STATUS (1 << 2)
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/*
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* Selected Technology. Becomes valid when an_status is 1.
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* The selection mode number (from 0 to 24) corresponds to the Technology
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* Ability (A0-A24) from the ability pages (see 4.3.2.3 page 13). The mode
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* selection is based on the matching technology abilities and priority.
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* A value of 31 is an invalid setting that indicates that no common technology
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* could be resolved. The application should then inspect the base page results
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* to determine if the link is operable or not.
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*/
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#define AN_LT_WRAPPER_AN_LT_STATUS_AN_SELECT_MASK 0x000001F0
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#define AN_LT_WRAPPER_AN_LT_STATUS_AN_SELECT_SHIFT 4
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/*
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* If set to 1, the Arbitration State Machine reached the TRANSMIT_DISABLE state
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*/
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#define AN_LT_WRAPPER_AN_LT_STATUS_AN_TR_DIS_STATUS (1 << 16)
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/*
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* FEC Enable. Asserts when autonegotiation base page exchange identified both
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* link partners advertising FEC capability and at least one is requesting FEC.
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* The signal stays constant following base page exchange until autonegotiation
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* is disabled or restarted.
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* Note: the information can also be extracted from the base page exchange or
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* the BP_ETH_STATUS register.
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*/
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#define AN_LT_WRAPPER_AN_LT_STATUS_FEC_ENA (1 << 17)
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/*
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* Link Training Frame Lock. If set to 1 the training frame delineation has been
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* acquired.
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*/
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#define AN_LT_WRAPPER_AN_LT_STATUS_LT_LOCK (1 << 20)
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/*
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* If set to 0, link-training is in progress, if set to 1, the training is
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* completed and the PCS datapath has been enabled (phy_los_out no longer
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* gated).
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*/
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#define AN_LT_WRAPPER_AN_LT_STATUS_LT_STATUS (1 << 21)
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/*
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* If set to 1, link-training is enabled on the link. It represents the enable
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* control bit PMD Control.taining enable. When set to 1, the signal lt_status
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* is valid
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*/
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#define AN_LT_WRAPPER_AN_LT_STATUS_LT_VAL (1 << 22)
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#ifdef __cplusplus
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}
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#endif
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#endif /* __AL_HAL_AN_LT_wrapper_REGS_H__ */
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/** @} end of ... group */
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