715 lines
19 KiB
C
715 lines
19 KiB
C
/*-
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* Copyright (c) 2005 M. Warner Losh
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* Copyright (c) 2005 Olivier Houchard
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* Copyright (c) 2012 Thomas Skibo
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* A driver for the Cadence AMBA UART as used by the Xilinx Zynq-7000.
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*
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* Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
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* (v1.4) November 16, 2012. Xilinx doc UG585. UART is covered in Ch. 19
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* and register definitions are in appendix B.33.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/cons.h>
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#include <sys/tty.h>
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#include <machine/bus.h>
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#include <dev/uart/uart.h>
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#include <dev/uart/uart_cpu.h>
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#include <dev/uart/uart_cpu_fdt.h>
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#include <dev/uart/uart_bus.h>
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#include "uart_if.h"
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#define UART_FIFO_SIZE 64
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#define RD4(bas, reg) \
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bus_space_read_4((bas)->bst, (bas)->bsh, uart_regofs((bas), (reg)))
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#define WR4(bas, reg, value) \
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bus_space_write_4((bas)->bst, (bas)->bsh, uart_regofs((bas), (reg)), \
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(value))
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/* Register definitions for Cadence UART Controller.
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*/
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#define CDNC_UART_CTRL_REG 0x00 /* Control Register. */
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#define CDNC_UART_CTRL_REG_STOPBRK (1<<8)
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#define CDNC_UART_CTRL_REG_STARTBRK (1<<7)
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#define CDNC_UART_CTRL_REG_TORST (1<<6)
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#define CDNC_UART_CTRL_REG_TX_DIS (1<<5)
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#define CDNC_UART_CTRL_REG_TX_EN (1<<4)
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#define CDNC_UART_CTRL_REG_RX_DIS (1<<3)
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#define CDNC_UART_CTRL_REG_RX_EN (1<<2)
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#define CDNC_UART_CTRL_REG_TXRST (1<<1)
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#define CDNC_UART_CTRL_REG_RXRST (1<<0)
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#define CDNC_UART_MODE_REG 0x04 /* Mode Register. */
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#define CDNC_UART_MODE_REG_CHMOD_R_LOOP (3<<8) /* [9:8] - channel mode */
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#define CDNC_UART_MODE_REG_CHMOD_L_LOOP (2<<8)
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#define CDNC_UART_MODE_REG_CHMOD_AUTECHO (1<<8)
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#define CDNC_UART_MODE_REG_STOP2 (2<<6) /* [7:6] - stop bits */
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#define CDNC_UART_MODE_REG_PAR_NONE (4<<3) /* [5:3] - parity type */
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#define CDNC_UART_MODE_REG_PAR_MARK (3<<3)
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#define CDNC_UART_MODE_REG_PAR_SPACE (2<<3)
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#define CDNC_UART_MODE_REG_PAR_ODD (1<<3)
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#define CDNC_UART_MODE_REG_PAR_EVEN (0<<3)
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#define CDNC_UART_MODE_REG_6BIT (3<<1) /* [2:1] - character len */
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#define CDNC_UART_MODE_REG_7BIT (2<<1)
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#define CDNC_UART_MODE_REG_8BIT (0<<1)
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#define CDNC_UART_MODE_REG_CLKSEL (1<<0)
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#define CDNC_UART_IEN_REG 0x08 /* Interrupt registers. */
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#define CDNC_UART_IDIS_REG 0x0C
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#define CDNC_UART_IMASK_REG 0x10
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#define CDNC_UART_ISTAT_REG 0x14
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#define CDNC_UART_INT_TXOVR (1<<12)
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#define CDNC_UART_INT_TXNRLYFUL (1<<11) /* tx "nearly" full */
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#define CDNC_UART_INT_TXTRIG (1<<10)
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#define CDNC_UART_INT_DMSI (1<<9) /* delta modem status */
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#define CDNC_UART_INT_RXTMOUT (1<<8)
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#define CDNC_UART_INT_PARITY (1<<7)
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#define CDNC_UART_INT_FRAMING (1<<6)
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#define CDNC_UART_INT_RXOVR (1<<5)
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#define CDNC_UART_INT_TXFULL (1<<4)
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#define CDNC_UART_INT_TXEMPTY (1<<3)
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#define CDNC_UART_INT_RXFULL (1<<2)
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#define CDNC_UART_INT_RXEMPTY (1<<1)
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#define CDNC_UART_INT_RXTRIG (1<<0)
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#define CDNC_UART_INT_ALL 0x1FFF
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#define CDNC_UART_BAUDGEN_REG 0x18
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#define CDNC_UART_RX_TIMEO_REG 0x1C
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#define CDNC_UART_RX_WATER_REG 0x20
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#define CDNC_UART_MODEM_CTRL_REG 0x24
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#define CDNC_UART_MODEM_CTRL_REG_FCM (1<<5) /* automatic flow control */
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#define CDNC_UART_MODEM_CTRL_REG_RTS (1<<1)
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#define CDNC_UART_MODEM_CTRL_REG_DTR (1<<0)
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#define CDNC_UART_MODEM_STAT_REG 0x28
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#define CDNC_UART_MODEM_STAT_REG_FCMS (1<<8) /* flow control mode (rw) */
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#define CDNC_UART_MODEM_STAT_REG_DCD (1<<7)
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#define CDNC_UART_MODEM_STAT_REG_RI (1<<6)
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#define CDNC_UART_MODEM_STAT_REG_DSR (1<<5)
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#define CDNC_UART_MODEM_STAT_REG_CTS (1<<4)
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#define CDNC_UART_MODEM_STAT_REG_DDCD (1<<3) /* change in DCD (w1tc) */
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#define CDNC_UART_MODEM_STAT_REG_TERI (1<<2) /* trail edge ring (w1tc) */
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#define CDNC_UART_MODEM_STAT_REG_DDSR (1<<1) /* change in DSR (w1tc) */
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#define CDNC_UART_MODEM_STAT_REG_DCTS (1<<0) /* change in CTS (w1tc) */
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#define CDNC_UART_CHAN_STAT_REG 0x2C /* Channel status register. */
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#define CDNC_UART_CHAN_STAT_REG_TXNRLYFUL (1<<14) /* tx "nearly" full */
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#define CDNC_UART_CHAN_STAT_REG_TXTRIG (1<<13)
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#define CDNC_UART_CHAN_STAT_REG_FDELT (1<<12)
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#define CDNC_UART_CHAN_STAT_REG_TXACTIVE (1<<11)
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#define CDNC_UART_CHAN_STAT_REG_RXACTIVE (1<<10)
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#define CDNC_UART_CHAN_STAT_REG_TXFULL (1<<4)
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#define CDNC_UART_CHAN_STAT_REG_TXEMPTY (1<<3)
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#define CDNC_UART_CHAN_STAT_REG_RXEMPTY (1<<1)
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#define CDNC_UART_CHAN_STAT_REG_RXTRIG (1<<0)
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#define CDNC_UART_FIFO 0x30 /* Data FIFO (tx and rx) */
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#define CDNC_UART_BAUDDIV_REG 0x34
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#define CDNC_UART_FLOWDEL_REG 0x38
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#define CDNC_UART_TX_WATER_REG 0x44
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/*
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* Low-level UART interface.
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*/
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static int cdnc_uart_probe(struct uart_bas *bas);
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static void cdnc_uart_init(struct uart_bas *bas, int, int, int, int);
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static void cdnc_uart_term(struct uart_bas *bas);
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static void cdnc_uart_putc(struct uart_bas *bas, int);
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static int cdnc_uart_rxready(struct uart_bas *bas);
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static int cdnc_uart_getc(struct uart_bas *bas, struct mtx *mtx);
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extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
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static struct uart_ops cdnc_uart_ops = {
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.probe = cdnc_uart_probe,
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.init = cdnc_uart_init,
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.term = cdnc_uart_term,
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.putc = cdnc_uart_putc,
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.rxready = cdnc_uart_rxready,
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.getc = cdnc_uart_getc,
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};
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#define SIGCHG(c, i, s, d) \
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if (c) { \
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i |= (i & s) ? s : s | d; \
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} else { \
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i = (i & s) ? (i & ~s) | d : i; \
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}
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static int
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cdnc_uart_probe(struct uart_bas *bas)
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{
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return (0);
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}
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static int
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cdnc_uart_set_baud(struct uart_bas *bas, int baudrate)
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{
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uint32_t baudgen, bauddiv;
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uint32_t best_bauddiv, best_baudgen, best_error;
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uint32_t baud_out, err;
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best_bauddiv = 0;
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best_baudgen = 0;
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best_error = ~0;
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/* Try all possible bauddiv values and pick best match. */
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for (bauddiv = 4; bauddiv <= 255; bauddiv++) {
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baudgen = (bas->rclk + (baudrate * (bauddiv + 1)) / 2) /
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(baudrate * (bauddiv + 1));
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if (baudgen < 1 || baudgen > 0xffff)
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continue;
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baud_out = bas->rclk / (baudgen * (bauddiv + 1));
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err = baud_out > baudrate ?
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baud_out - baudrate : baudrate - baud_out;
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if (err < best_error) {
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best_error = err;
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best_bauddiv = bauddiv;
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best_baudgen = baudgen;
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}
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}
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if (best_bauddiv > 0) {
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WR4(bas, CDNC_UART_BAUDDIV_REG, best_bauddiv);
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WR4(bas, CDNC_UART_BAUDGEN_REG, best_baudgen);
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return (0);
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} else
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return (-1); /* out of range */
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}
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static int
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cdnc_uart_set_params(struct uart_bas *bas, int baudrate, int databits,
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int stopbits, int parity)
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{
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uint32_t mode_reg_value = 0;
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switch (databits) {
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case 6:
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mode_reg_value |= CDNC_UART_MODE_REG_6BIT;
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break;
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case 7:
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mode_reg_value |= CDNC_UART_MODE_REG_7BIT;
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break;
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case 8:
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default:
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mode_reg_value |= CDNC_UART_MODE_REG_8BIT;
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break;
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}
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if (stopbits == 2)
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mode_reg_value |= CDNC_UART_MODE_REG_STOP2;
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switch (parity) {
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case UART_PARITY_MARK:
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mode_reg_value |= CDNC_UART_MODE_REG_PAR_MARK;
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break;
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case UART_PARITY_SPACE:
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mode_reg_value |= CDNC_UART_MODE_REG_PAR_SPACE;
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break;
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case UART_PARITY_ODD:
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mode_reg_value |= CDNC_UART_MODE_REG_PAR_ODD;
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break;
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case UART_PARITY_EVEN:
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mode_reg_value |= CDNC_UART_MODE_REG_PAR_EVEN;
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break;
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case UART_PARITY_NONE:
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default:
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mode_reg_value |= CDNC_UART_MODE_REG_PAR_NONE;
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break;
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}
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WR4(bas, CDNC_UART_MODE_REG, mode_reg_value);
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if (baudrate > 0 && cdnc_uart_set_baud(bas, baudrate) < 0)
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return (EINVAL);
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return(0);
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}
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static void
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cdnc_uart_hw_init(struct uart_bas *bas)
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{
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/* Reset RX and TX. */
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WR4(bas, CDNC_UART_CTRL_REG,
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CDNC_UART_CTRL_REG_RXRST | CDNC_UART_CTRL_REG_TXRST);
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/* Interrupts all off. */
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WR4(bas, CDNC_UART_IDIS_REG, CDNC_UART_INT_ALL);
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WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_ALL);
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/* Clear delta bits. */
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WR4(bas, CDNC_UART_MODEM_STAT_REG,
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CDNC_UART_MODEM_STAT_REG_DDCD | CDNC_UART_MODEM_STAT_REG_TERI |
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CDNC_UART_MODEM_STAT_REG_DDSR | CDNC_UART_MODEM_STAT_REG_DCTS);
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/* RX FIFO water level, stale timeout */
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WR4(bas, CDNC_UART_RX_WATER_REG, UART_FIFO_SIZE/2);
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WR4(bas, CDNC_UART_RX_TIMEO_REG, 10);
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/* TX FIFO water level (not used.) */
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WR4(bas, CDNC_UART_TX_WATER_REG, UART_FIFO_SIZE/2);
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/* Bring RX and TX online. */
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WR4(bas, CDNC_UART_CTRL_REG,
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CDNC_UART_CTRL_REG_RX_EN | CDNC_UART_CTRL_REG_TX_EN |
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CDNC_UART_CTRL_REG_TORST | CDNC_UART_CTRL_REG_STOPBRK);
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/* Set DTR and RTS. */
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WR4(bas, CDNC_UART_MODEM_CTRL_REG, CDNC_UART_MODEM_CTRL_REG_DTR |
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CDNC_UART_MODEM_CTRL_REG_RTS);
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}
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/*
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* Initialize this device for use as a console.
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*/
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static void
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cdnc_uart_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
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int parity)
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{
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/* Initialize hardware. */
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cdnc_uart_hw_init(bas);
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/* Set baudrate, parameters. */
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(void)cdnc_uart_set_params(bas, baudrate, databits, stopbits, parity);
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}
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/*
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* Free resources now that we're no longer the console. This appears to
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* be never called, and I'm unsure quite what to do if I am called.
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*/
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static void
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cdnc_uart_term(struct uart_bas *bas)
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{
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/* XXX */
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}
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/*
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* Put a character of console output (so we do it here polling rather than
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* interrutp driven).
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*/
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static void
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cdnc_uart_putc(struct uart_bas *bas, int c)
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{
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/* Wait for room. */
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while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) &
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CDNC_UART_CHAN_STAT_REG_TXFULL) != 0)
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;
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WR4(bas, CDNC_UART_FIFO, c);
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while ((RD4(bas,CDNC_UART_CHAN_STAT_REG) &
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CDNC_UART_CHAN_STAT_REG_TXEMPTY) == 0)
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;
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}
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/*
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* Check for a character available.
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*/
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static int
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cdnc_uart_rxready(struct uart_bas *bas)
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{
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return ((RD4(bas, CDNC_UART_CHAN_STAT_REG) &
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CDNC_UART_CHAN_STAT_REG_RXEMPTY) == 0);
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}
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/*
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* Block waiting for a character.
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*/
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static int
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cdnc_uart_getc(struct uart_bas *bas, struct mtx *mtx)
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{
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int c;
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uart_lock(mtx);
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while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) &
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CDNC_UART_CHAN_STAT_REG_RXEMPTY) != 0) {
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uart_unlock(mtx);
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DELAY(4);
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uart_lock(mtx);
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}
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c = RD4(bas, CDNC_UART_FIFO);
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uart_unlock(mtx);
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c &= 0xff;
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return (c);
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}
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/*****************************************************************************/
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/*
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* High-level UART interface.
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*/
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static int cdnc_uart_bus_probe(struct uart_softc *sc);
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static int cdnc_uart_bus_attach(struct uart_softc *sc);
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static int cdnc_uart_bus_flush(struct uart_softc *, int);
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static int cdnc_uart_bus_getsig(struct uart_softc *);
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static int cdnc_uart_bus_ioctl(struct uart_softc *, int, intptr_t);
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static int cdnc_uart_bus_ipend(struct uart_softc *);
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static int cdnc_uart_bus_param(struct uart_softc *, int, int, int, int);
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static int cdnc_uart_bus_receive(struct uart_softc *);
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static int cdnc_uart_bus_setsig(struct uart_softc *, int);
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static int cdnc_uart_bus_transmit(struct uart_softc *);
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static void cdnc_uart_bus_grab(struct uart_softc *);
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static void cdnc_uart_bus_ungrab(struct uart_softc *);
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static kobj_method_t cdnc_uart_bus_methods[] = {
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KOBJMETHOD(uart_probe, cdnc_uart_bus_probe),
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KOBJMETHOD(uart_attach, cdnc_uart_bus_attach),
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KOBJMETHOD(uart_flush, cdnc_uart_bus_flush),
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KOBJMETHOD(uart_getsig, cdnc_uart_bus_getsig),
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KOBJMETHOD(uart_ioctl, cdnc_uart_bus_ioctl),
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KOBJMETHOD(uart_ipend, cdnc_uart_bus_ipend),
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KOBJMETHOD(uart_param, cdnc_uart_bus_param),
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KOBJMETHOD(uart_receive, cdnc_uart_bus_receive),
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KOBJMETHOD(uart_setsig, cdnc_uart_bus_setsig),
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KOBJMETHOD(uart_transmit, cdnc_uart_bus_transmit),
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KOBJMETHOD(uart_grab, cdnc_uart_bus_grab),
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KOBJMETHOD(uart_ungrab, cdnc_uart_bus_ungrab),
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KOBJMETHOD_END
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};
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int
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cdnc_uart_bus_probe(struct uart_softc *sc)
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{
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sc->sc_txfifosz = UART_FIFO_SIZE;
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sc->sc_rxfifosz = UART_FIFO_SIZE;
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sc->sc_hwiflow = 0;
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sc->sc_hwoflow = 0;
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device_set_desc(sc->sc_dev, "Cadence UART");
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return (0);
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}
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static int
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cdnc_uart_bus_attach(struct uart_softc *sc)
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{
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struct uart_bas *bas = &sc->sc_bas;
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struct uart_devinfo *di;
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if (sc->sc_sysdev != NULL) {
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di = sc->sc_sysdev;
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(void)cdnc_uart_set_params(bas, di->baudrate, di->databits,
|
|
di->stopbits, di->parity);
|
|
} else
|
|
cdnc_uart_hw_init(bas);
|
|
|
|
(void)cdnc_uart_bus_getsig(sc);
|
|
|
|
/* Enable interrupts. */
|
|
WR4(bas, CDNC_UART_IEN_REG,
|
|
CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT |
|
|
CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR |
|
|
CDNC_UART_INT_DMSI);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
cdnc_uart_bus_transmit(struct uart_softc *sc)
|
|
{
|
|
int i;
|
|
struct uart_bas *bas = &sc->sc_bas;
|
|
|
|
uart_lock(sc->sc_hwmtx);
|
|
|
|
/* Clear sticky TXEMPTY status bit. */
|
|
WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_TXEMPTY);
|
|
|
|
for (i = 0; i < sc->sc_txdatasz; i++)
|
|
WR4(bas, CDNC_UART_FIFO, sc->sc_txbuf[i]);
|
|
|
|
/* Enable TX empty interrupt. */
|
|
WR4(bas, CDNC_UART_IEN_REG, CDNC_UART_INT_TXEMPTY);
|
|
sc->sc_txbusy = 1;
|
|
|
|
uart_unlock(sc->sc_hwmtx);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
cdnc_uart_bus_setsig(struct uart_softc *sc, int sig)
|
|
{
|
|
struct uart_bas *bas = &sc->sc_bas;
|
|
uint32_t new, old, modem_ctrl;
|
|
|
|
do {
|
|
old = sc->sc_hwsig;
|
|
new = old;
|
|
if (sig & SER_DDTR) {
|
|
SIGCHG(sig & SER_DTR, new, SER_DTR, SER_DDTR);
|
|
}
|
|
if (sig & SER_DRTS) {
|
|
SIGCHG(sig & SER_RTS, new, SER_RTS, SER_DRTS);
|
|
}
|
|
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
|
|
uart_lock(sc->sc_hwmtx);
|
|
modem_ctrl = RD4(bas, CDNC_UART_MODEM_CTRL_REG) &
|
|
~(CDNC_UART_MODEM_CTRL_REG_DTR | CDNC_UART_MODEM_CTRL_REG_RTS);
|
|
if ((new & SER_DTR) != 0)
|
|
modem_ctrl |= CDNC_UART_MODEM_CTRL_REG_DTR;
|
|
if ((new & SER_RTS) != 0)
|
|
modem_ctrl |= CDNC_UART_MODEM_CTRL_REG_RTS;
|
|
WR4(bas, CDNC_UART_MODEM_CTRL_REG, modem_ctrl);
|
|
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
cdnc_uart_bus_receive(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas = &sc->sc_bas;
|
|
uint32_t status;
|
|
int c, c_status = 0;
|
|
|
|
uart_lock(sc->sc_hwmtx);
|
|
|
|
/* Check for parity or framing errors and clear the status bits. */
|
|
status = RD4(bas, CDNC_UART_ISTAT_REG);
|
|
if ((status & (CDNC_UART_INT_FRAMING | CDNC_UART_INT_PARITY)) != 0) {
|
|
WR4(bas, CDNC_UART_ISTAT_REG,
|
|
status & (CDNC_UART_INT_FRAMING | CDNC_UART_INT_PARITY));
|
|
if ((status & CDNC_UART_INT_PARITY) != 0)
|
|
c_status |= UART_STAT_PARERR;
|
|
if ((status & CDNC_UART_INT_FRAMING) != 0)
|
|
c_status |= UART_STAT_FRAMERR;
|
|
}
|
|
|
|
while ((RD4(bas, CDNC_UART_CHAN_STAT_REG) &
|
|
CDNC_UART_CHAN_STAT_REG_RXEMPTY) == 0) {
|
|
c = RD4(bas, CDNC_UART_FIFO) & 0xff;
|
|
#ifdef KDB
|
|
/* Detect break and drop into debugger. */
|
|
if (c == 0 && (c_status & UART_STAT_FRAMERR) != 0 &&
|
|
sc->sc_sysdev != NULL &&
|
|
sc->sc_sysdev->type == UART_DEV_CONSOLE) {
|
|
kdb_break();
|
|
WR4(bas, CDNC_UART_ISTAT_REG, CDNC_UART_INT_FRAMING);
|
|
}
|
|
#endif
|
|
uart_rx_put(sc, c | c_status);
|
|
}
|
|
|
|
uart_unlock(sc->sc_hwmtx);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
cdnc_uart_bus_param(struct uart_softc *sc, int baudrate, int databits,
|
|
int stopbits, int parity)
|
|
{
|
|
|
|
return (cdnc_uart_set_params(&sc->sc_bas, baudrate,
|
|
databits, stopbits, parity));
|
|
}
|
|
|
|
static int
|
|
cdnc_uart_bus_ipend(struct uart_softc *sc)
|
|
{
|
|
int ipend = 0;
|
|
struct uart_bas *bas = &sc->sc_bas;
|
|
uint32_t istatus;
|
|
|
|
uart_lock(sc->sc_hwmtx);
|
|
|
|
istatus = RD4(bas, CDNC_UART_ISTAT_REG);
|
|
|
|
/* Clear interrupt bits. */
|
|
WR4(bas, CDNC_UART_ISTAT_REG, istatus &
|
|
(CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT |
|
|
CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR |
|
|
CDNC_UART_INT_TXEMPTY | CDNC_UART_INT_DMSI));
|
|
|
|
/* Receive data. */
|
|
if ((istatus & (CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT)) != 0)
|
|
ipend |= SER_INT_RXREADY;
|
|
|
|
/* Transmit fifo empty. */
|
|
if (sc->sc_txbusy && (istatus & CDNC_UART_INT_TXEMPTY) != 0) {
|
|
/* disable txempty interrupt. */
|
|
WR4(bas, CDNC_UART_IDIS_REG, CDNC_UART_INT_TXEMPTY);
|
|
ipend |= SER_INT_TXIDLE;
|
|
}
|
|
|
|
/* TX Overflow. */
|
|
if ((istatus & CDNC_UART_INT_TXOVR) != 0)
|
|
ipend |= SER_INT_OVERRUN;
|
|
|
|
/* RX Overflow. */
|
|
if ((istatus & CDNC_UART_INT_RXOVR) != 0)
|
|
ipend |= SER_INT_OVERRUN;
|
|
|
|
/* Modem signal change. */
|
|
if ((istatus & CDNC_UART_INT_DMSI) != 0) {
|
|
WR4(bas, CDNC_UART_MODEM_STAT_REG,
|
|
CDNC_UART_MODEM_STAT_REG_DDCD |
|
|
CDNC_UART_MODEM_STAT_REG_TERI |
|
|
CDNC_UART_MODEM_STAT_REG_DDSR |
|
|
CDNC_UART_MODEM_STAT_REG_DCTS);
|
|
ipend |= SER_INT_SIGCHG;
|
|
}
|
|
|
|
uart_unlock(sc->sc_hwmtx);
|
|
return (ipend);
|
|
}
|
|
|
|
static int
|
|
cdnc_uart_bus_flush(struct uart_softc *sc, int what)
|
|
{
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
cdnc_uart_bus_getsig(struct uart_softc *sc)
|
|
{
|
|
struct uart_bas *bas = &sc->sc_bas;
|
|
uint32_t new, old, sig;
|
|
uint8_t modem_status;
|
|
|
|
do {
|
|
old = sc->sc_hwsig;
|
|
sig = old;
|
|
uart_lock(sc->sc_hwmtx);
|
|
modem_status = RD4(bas, CDNC_UART_MODEM_STAT_REG);
|
|
uart_unlock(sc->sc_hwmtx);
|
|
SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_DSR,
|
|
sig, SER_DSR, SER_DDSR);
|
|
SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_CTS,
|
|
sig, SER_CTS, SER_DCTS);
|
|
SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_DCD,
|
|
sig, SER_DCD, SER_DDCD);
|
|
SIGCHG(modem_status & CDNC_UART_MODEM_STAT_REG_RI,
|
|
sig, SER_RI, SER_DRI);
|
|
new = sig & ~SER_MASK_DELTA;
|
|
} while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
|
|
return (sig);
|
|
}
|
|
|
|
static int
|
|
cdnc_uart_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
|
|
{
|
|
struct uart_bas *bas = &sc->sc_bas;
|
|
uint32_t uart_ctrl, modem_ctrl;
|
|
int error = 0;
|
|
|
|
uart_lock(sc->sc_hwmtx);
|
|
|
|
switch (request) {
|
|
case UART_IOCTL_BREAK:
|
|
uart_ctrl = RD4(bas, CDNC_UART_CTRL_REG);
|
|
if (data) {
|
|
uart_ctrl |= CDNC_UART_CTRL_REG_STARTBRK;
|
|
uart_ctrl &= ~CDNC_UART_CTRL_REG_STOPBRK;
|
|
} else {
|
|
uart_ctrl |= CDNC_UART_CTRL_REG_STOPBRK;
|
|
uart_ctrl &= ~CDNC_UART_CTRL_REG_STARTBRK;
|
|
}
|
|
WR4(bas, CDNC_UART_CTRL_REG, uart_ctrl);
|
|
break;
|
|
case UART_IOCTL_IFLOW:
|
|
modem_ctrl = RD4(bas, CDNC_UART_MODEM_CTRL_REG);
|
|
if (data)
|
|
modem_ctrl |= CDNC_UART_MODEM_CTRL_REG_RTS;
|
|
else
|
|
modem_ctrl &= ~CDNC_UART_MODEM_CTRL_REG_RTS;
|
|
WR4(bas, CDNC_UART_MODEM_CTRL_REG, modem_ctrl);
|
|
break;
|
|
default:
|
|
error = EINVAL;
|
|
break;
|
|
}
|
|
|
|
uart_unlock(sc->sc_hwmtx);
|
|
|
|
return (error);
|
|
}
|
|
|
|
static void
|
|
cdnc_uart_bus_grab(struct uart_softc *sc)
|
|
{
|
|
|
|
/* Enable interrupts. */
|
|
WR4(&sc->sc_bas, CDNC_UART_IEN_REG,
|
|
CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR |
|
|
CDNC_UART_INT_DMSI);
|
|
}
|
|
|
|
static void
|
|
cdnc_uart_bus_ungrab(struct uart_softc *sc)
|
|
{
|
|
|
|
/* Enable interrupts. */
|
|
WR4(&sc->sc_bas, CDNC_UART_IEN_REG,
|
|
CDNC_UART_INT_RXTRIG | CDNC_UART_INT_RXTMOUT |
|
|
CDNC_UART_INT_TXOVR | CDNC_UART_INT_RXOVR |
|
|
CDNC_UART_INT_DMSI);
|
|
}
|
|
|
|
static struct uart_class uart_cdnc_class = {
|
|
"cdnc_uart",
|
|
cdnc_uart_bus_methods,
|
|
sizeof(struct uart_softc),
|
|
.uc_ops = &cdnc_uart_ops,
|
|
.uc_range = 8
|
|
};
|
|
|
|
static struct ofw_compat_data compat_data[] = {
|
|
{"cadence,uart", (uintptr_t)&uart_cdnc_class},
|
|
{NULL, (uintptr_t)NULL},
|
|
};
|
|
UART_FDT_CLASS_AND_DEVICE(compat_data);
|