399 lines
10 KiB
C
399 lines
10 KiB
C
/*-
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* Copyright (c) 2013 Thomas Skibo
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* A GPIO driver for Xilinx Zynq-7000.
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*
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* The GPIO peripheral on Zynq allows controlling 114 general purpose I/Os.
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*
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* Pins 53-0 are sent to the MIO. Any MIO pins not used by a PS peripheral are
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* available as a GPIO pin. Pins 64-127 are sent to the PL (FPGA) section of
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* Zynq as EMIO signals.
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*
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* The hardware provides a way to use IOs as interrupt sources but the
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* gpio framework doesn't seem to have hooks for this.
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*
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* Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
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* (v1.4) November 16, 2012. Xilinx doc UG585. GPIO is covered in
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* chater 14. Register definitions are in appendix B.19.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/gpio.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/stdarg.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/gpio/gpiobusvar.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "gpio_if.h"
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#define NUMBANKS 4
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#define MAXPIN (32*NUMBANKS)
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#define MIO_PIN 0 /* pins 0-53 go to MIO */
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#define NUM_MIO_PINS 54
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#define EMIO_PIN 64 /* pins 64-127 go to PL */
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#define NUM_EMIO_PINS 64
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#define VALID_PIN(u) (((u) >= MIO_PIN && (u) < MIO_PIN + NUM_MIO_PINS) || \
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((u) >= EMIO_PIN && (u) < EMIO_PIN + NUM_EMIO_PINS))
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#define ZGPIO_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
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#define ZGPIO_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
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#define ZGPIO_LOCK_INIT(sc) \
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mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
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"gpio", MTX_DEF)
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#define ZGPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
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struct zy7_gpio_softc {
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device_t dev;
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device_t busdev;
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struct mtx sc_mtx;
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struct resource *mem_res; /* Memory resource */
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};
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#define WR4(sc, off, val) bus_write_4((sc)->mem_res, (off), (val))
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#define RD4(sc, off) bus_read_4((sc)->mem_res, (off))
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/* Xilinx Zynq-7000 GPIO register definitions:
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*/
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#define ZY7_GPIO_MASK_DATA_LSW(b) (0x0000+8*(b)) /* maskable wr lo */
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#define ZY7_GPIO_MASK_DATA_MSW(b) (0x0004+8*(b)) /* maskable wr hi */
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#define ZY7_GPIO_DATA(b) (0x0040+4*(b)) /* in/out data */
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#define ZY7_GPIO_DATA_RO(b) (0x0060+4*(b)) /* input data */
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#define ZY7_GPIO_DIRM(b) (0x0204+0x40*(b)) /* direction mode */
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#define ZY7_GPIO_OEN(b) (0x0208+0x40*(b)) /* output enable */
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#define ZY7_GPIO_INT_MASK(b) (0x020c+0x40*(b)) /* int mask */
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#define ZY7_GPIO_INT_EN(b) (0x0210+0x40*(b)) /* int enable */
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#define ZY7_GPIO_INT_DIS(b) (0x0214+0x40*(b)) /* int disable */
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#define ZY7_GPIO_INT_STAT(b) (0x0218+0x40*(b)) /* int status */
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#define ZY7_GPIO_INT_TYPE(b) (0x021c+0x40*(b)) /* int type */
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#define ZY7_GPIO_INT_POLARITY(b) (0x0220+0x40*(b)) /* int polarity */
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#define ZY7_GPIO_INT_ANY(b) (0x0224+0x40*(b)) /* any edge */
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static device_t
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zy7_gpio_get_bus(device_t dev)
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{
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struct zy7_gpio_softc *sc;
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sc = device_get_softc(dev);
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return (sc->busdev);
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}
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static int
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zy7_gpio_pin_max(device_t dev, int *maxpin)
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{
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*maxpin = MAXPIN;
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return (0);
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}
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/* Get a specific pin's capabilities. */
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static int
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zy7_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
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{
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if (!VALID_PIN(pin))
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return (EINVAL);
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*caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE);
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return (0);
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}
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/* Get a specific pin's name. */
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static int
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zy7_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
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{
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if (!VALID_PIN(pin))
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return (EINVAL);
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if (pin < NUM_MIO_PINS) {
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snprintf(name, GPIOMAXNAME, "MIO_%d", pin);
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name[GPIOMAXNAME - 1] = '\0';
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} else {
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snprintf(name, GPIOMAXNAME, "EMIO_%d", pin - EMIO_PIN);
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name[GPIOMAXNAME - 1] = '\0';
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}
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return (0);
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}
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/* Get a specific pin's current in/out/tri state. */
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static int
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zy7_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
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{
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struct zy7_gpio_softc *sc = device_get_softc(dev);
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if (!VALID_PIN(pin))
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return (EINVAL);
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ZGPIO_LOCK(sc);
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if ((RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & (1 << (pin & 31))) != 0) {
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/* output */
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if ((RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & (1 << (pin & 31))) == 0)
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*flags = (GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE);
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else
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*flags = GPIO_PIN_OUTPUT;
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} else
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/* input */
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*flags = GPIO_PIN_INPUT;
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ZGPIO_UNLOCK(sc);
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return (0);
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}
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/* Set a specific pin's in/out/tri state. */
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static int
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zy7_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
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{
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struct zy7_gpio_softc *sc = device_get_softc(dev);
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if (!VALID_PIN(pin))
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return (EINVAL);
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ZGPIO_LOCK(sc);
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if ((flags & GPIO_PIN_OUTPUT) != 0) {
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/* Output. Set or reset OEN too. */
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WR4(sc, ZY7_GPIO_DIRM(pin >> 5),
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RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) | (1 << (pin & 31)));
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if ((flags & GPIO_PIN_TRISTATE) != 0)
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WR4(sc, ZY7_GPIO_OEN(pin >> 5),
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RD4(sc, ZY7_GPIO_OEN(pin >> 5)) &
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~(1 << (pin & 31)));
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else
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WR4(sc, ZY7_GPIO_OEN(pin >> 5),
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RD4(sc, ZY7_GPIO_OEN(pin >> 5)) |
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(1 << (pin & 31)));
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} else {
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/* Input. Turn off OEN. */
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WR4(sc, ZY7_GPIO_DIRM(pin >> 5),
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RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & ~(1 << (pin & 31)));
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WR4(sc, ZY7_GPIO_OEN(pin >> 5),
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RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & ~(1 << (pin & 31)));
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}
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ZGPIO_UNLOCK(sc);
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return (0);
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}
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/* Set a specific output pin's value. */
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static int
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zy7_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
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{
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struct zy7_gpio_softc *sc = device_get_softc(dev);
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if (!VALID_PIN(pin) || value > 1)
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return (EINVAL);
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/* Fancy register tricks allow atomic set or reset. */
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if ((pin & 16) != 0)
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WR4(sc, ZY7_GPIO_MASK_DATA_MSW(pin >> 5),
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(0xffff0000 ^ (0x10000 << (pin & 15))) |
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(value << (pin & 15)));
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else
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WR4(sc, ZY7_GPIO_MASK_DATA_LSW(pin >> 5),
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(0xffff0000 ^ (0x10000 << (pin & 15))) |
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(value << (pin & 15)));
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return (0);
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}
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/* Get a specific pin's input value. */
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static int
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zy7_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
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{
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struct zy7_gpio_softc *sc = device_get_softc(dev);
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if (!VALID_PIN(pin))
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return (EINVAL);
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*value = (RD4(sc, ZY7_GPIO_DATA_RO(pin >> 5)) >> (pin & 31)) & 1;
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return (0);
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}
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/* Toggle a pin's output value. */
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static int
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zy7_gpio_pin_toggle(device_t dev, uint32_t pin)
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{
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struct zy7_gpio_softc *sc = device_get_softc(dev);
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if (!VALID_PIN(pin))
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return (EINVAL);
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ZGPIO_LOCK(sc);
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WR4(sc, ZY7_GPIO_DATA(pin >> 5),
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RD4(sc, ZY7_GPIO_DATA(pin >> 5)) ^ (1 << (pin & 31)));
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ZGPIO_UNLOCK(sc);
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return (0);
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}
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static int
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zy7_gpio_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "xlnx,zy7_gpio"))
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return (ENXIO);
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device_set_desc(dev, "Zynq-7000 GPIO driver");
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return (0);
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}
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static void
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zy7_gpio_hw_reset(struct zy7_gpio_softc *sc)
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{
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int i;
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for (i = 0; i < NUMBANKS; i++) {
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WR4(sc, ZY7_GPIO_DATA(i), 0);
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WR4(sc, ZY7_GPIO_DIRM(i), 0);
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WR4(sc, ZY7_GPIO_OEN(i), 0);
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WR4(sc, ZY7_GPIO_INT_DIS(i), 0xffffffff);
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WR4(sc, ZY7_GPIO_INT_POLARITY(i), 0);
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WR4(sc, ZY7_GPIO_INT_TYPE(i),
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i == 1 ? 0x003fffff : 0xffffffff);
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WR4(sc, ZY7_GPIO_INT_ANY(i), 0);
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WR4(sc, ZY7_GPIO_INT_STAT(i), 0xffffffff);
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}
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}
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static int zy7_gpio_detach(device_t dev);
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static int
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zy7_gpio_attach(device_t dev)
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{
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struct zy7_gpio_softc *sc = device_get_softc(dev);
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int rid;
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sc->dev = dev;
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ZGPIO_LOCK_INIT(sc);
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/* Allocate memory. */
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rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev,
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SYS_RES_MEMORY, &rid, RF_ACTIVE);
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if (sc->mem_res == NULL) {
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device_printf(dev, "Can't allocate memory for device");
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zy7_gpio_detach(dev);
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return (ENOMEM);
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}
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/* Completely reset. */
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zy7_gpio_hw_reset(sc);
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sc->busdev = gpiobus_attach_bus(dev);
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if (sc->busdev == NULL) {
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zy7_gpio_detach(dev);
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return (ENOMEM);
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}
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return (0);
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}
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static int
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zy7_gpio_detach(device_t dev)
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{
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struct zy7_gpio_softc *sc = device_get_softc(dev);
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gpiobus_detach_bus(dev);
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if (sc->mem_res != NULL) {
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/* Release memory resource. */
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bus_release_resource(dev, SYS_RES_MEMORY,
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rman_get_rid(sc->mem_res), sc->mem_res);
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}
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ZGPIO_LOCK_DESTROY(sc);
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return (0);
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}
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static device_method_t zy7_gpio_methods[] = {
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/* device_if */
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DEVMETHOD(device_probe, zy7_gpio_probe),
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DEVMETHOD(device_attach, zy7_gpio_attach),
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DEVMETHOD(device_detach, zy7_gpio_detach),
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/* GPIO protocol */
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DEVMETHOD(gpio_get_bus, zy7_gpio_get_bus),
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DEVMETHOD(gpio_pin_max, zy7_gpio_pin_max),
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DEVMETHOD(gpio_pin_getname, zy7_gpio_pin_getname),
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DEVMETHOD(gpio_pin_getflags, zy7_gpio_pin_getflags),
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DEVMETHOD(gpio_pin_getcaps, zy7_gpio_pin_getcaps),
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DEVMETHOD(gpio_pin_setflags, zy7_gpio_pin_setflags),
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DEVMETHOD(gpio_pin_get, zy7_gpio_pin_get),
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DEVMETHOD(gpio_pin_set, zy7_gpio_pin_set),
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DEVMETHOD(gpio_pin_toggle, zy7_gpio_pin_toggle),
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DEVMETHOD_END
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};
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static driver_t zy7_gpio_driver = {
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"gpio",
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zy7_gpio_methods,
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sizeof(struct zy7_gpio_softc),
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};
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static devclass_t zy7_gpio_devclass;
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DRIVER_MODULE(zy7_gpio, simplebus, zy7_gpio_driver, zy7_gpio_devclass, \
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NULL, NULL);
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