2021-09-13 18:07:23 +03:00
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/*
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* ITS emulation for a GICv3-based system
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*
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* Copyright Linaro.org 2021
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*
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* Authors:
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* Shashi Mallela <shashi.mallela@linaro.org>
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or (at your
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* option) any later version. See the COPYING file in the top-level directory.
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*
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "hw/qdev-properties.h"
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#include "hw/intc/arm_gicv3_its_common.h"
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#include "gicv3_internal.h"
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#include "qom/object.h"
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#include "qapi/error.h"
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typedef struct GICv3ITSClass GICv3ITSClass;
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/* This is reusing the GICv3ITSState typedef from ARM_GICV3_ITS_COMMON */
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DECLARE_OBJ_CHECKERS(GICv3ITSState, GICv3ITSClass,
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ARM_GICV3_ITS, TYPE_ARM_GICV3_ITS)
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struct GICv3ITSClass {
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GICv3ITSCommonClass parent_class;
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void (*parent_reset)(DeviceState *dev);
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};
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2021-09-13 18:07:23 +03:00
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static uint64_t baser_base_addr(uint64_t value, uint32_t page_sz)
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{
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uint64_t result = 0;
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switch (page_sz) {
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case GITS_PAGE_SIZE_4K:
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case GITS_PAGE_SIZE_16K:
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result = FIELD_EX64(value, GITS_BASER, PHYADDR) << 12;
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break;
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case GITS_PAGE_SIZE_64K:
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result = FIELD_EX64(value, GITS_BASER, PHYADDRL_64K) << 16;
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result |= FIELD_EX64(value, GITS_BASER, PHYADDRH_64K) << 48;
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break;
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default:
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break;
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}
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return result;
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}
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/*
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* This function extracts the ITS Device and Collection table specific
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* parameters (like base_addr, size etc) from GITS_BASER register.
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* It is called during ITS enable and also during post_load migration
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*/
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static void extract_table_params(GICv3ITSState *s)
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{
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uint16_t num_pages = 0;
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uint8_t page_sz_type;
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uint8_t type;
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uint32_t page_sz = 0;
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uint64_t value;
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for (int i = 0; i < 8; i++) {
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value = s->baser[i];
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if (!value) {
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continue;
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}
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page_sz_type = FIELD_EX64(value, GITS_BASER, PAGESIZE);
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switch (page_sz_type) {
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case 0:
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page_sz = GITS_PAGE_SIZE_4K;
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break;
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case 1:
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page_sz = GITS_PAGE_SIZE_16K;
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break;
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case 2:
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case 3:
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page_sz = GITS_PAGE_SIZE_64K;
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break;
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default:
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g_assert_not_reached();
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}
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num_pages = FIELD_EX64(value, GITS_BASER, SIZE) + 1;
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type = FIELD_EX64(value, GITS_BASER, TYPE);
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switch (type) {
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case GITS_BASER_TYPE_DEVICE:
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memset(&s->dt, 0 , sizeof(s->dt));
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s->dt.valid = FIELD_EX64(value, GITS_BASER, VALID);
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if (!s->dt.valid) {
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return;
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}
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s->dt.page_sz = page_sz;
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s->dt.indirect = FIELD_EX64(value, GITS_BASER, INDIRECT);
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s->dt.entry_sz = FIELD_EX64(value, GITS_BASER, ENTRYSIZE);
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if (!s->dt.indirect) {
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s->dt.max_entries = (num_pages * page_sz) / s->dt.entry_sz;
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} else {
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s->dt.max_entries = (((num_pages * page_sz) /
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L1TABLE_ENTRY_SIZE) *
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(page_sz / s->dt.entry_sz));
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}
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s->dt.maxids.max_devids = (1UL << (FIELD_EX64(s->typer, GITS_TYPER,
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DEVBITS) + 1));
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s->dt.base_addr = baser_base_addr(value, page_sz);
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break;
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case GITS_BASER_TYPE_COLLECTION:
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memset(&s->ct, 0 , sizeof(s->ct));
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s->ct.valid = FIELD_EX64(value, GITS_BASER, VALID);
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/*
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* GITS_TYPER.HCC is 0 for this implementation
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* hence writes are discarded if ct.valid is 0
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*/
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if (!s->ct.valid) {
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return;
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}
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s->ct.page_sz = page_sz;
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s->ct.indirect = FIELD_EX64(value, GITS_BASER, INDIRECT);
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s->ct.entry_sz = FIELD_EX64(value, GITS_BASER, ENTRYSIZE);
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if (!s->ct.indirect) {
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s->ct.max_entries = (num_pages * page_sz) / s->ct.entry_sz;
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} else {
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s->ct.max_entries = (((num_pages * page_sz) /
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L1TABLE_ENTRY_SIZE) *
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(page_sz / s->ct.entry_sz));
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}
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if (FIELD_EX64(s->typer, GITS_TYPER, CIL)) {
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s->ct.maxids.max_collids = (1UL << (FIELD_EX64(s->typer,
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GITS_TYPER, CIDBITS) + 1));
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} else {
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/* 16-bit CollectionId supported when CIL == 0 */
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s->ct.maxids.max_collids = (1UL << 16);
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}
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s->ct.base_addr = baser_base_addr(value, page_sz);
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break;
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default:
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break;
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}
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}
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}
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static void extract_cmdq_params(GICv3ITSState *s)
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{
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uint16_t num_pages = 0;
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uint64_t value = s->cbaser;
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num_pages = FIELD_EX64(value, GITS_CBASER, SIZE) + 1;
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memset(&s->cq, 0 , sizeof(s->cq));
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s->cq.valid = FIELD_EX64(value, GITS_CBASER, VALID);
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if (s->cq.valid) {
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s->cq.max_entries = (num_pages * GITS_PAGE_SIZE_4K) /
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GITS_CMDQ_ENTRY_SIZE;
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s->cq.base_addr = FIELD_EX64(value, GITS_CBASER, PHYADDR);
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s->cq.base_addr <<= R_GITS_CBASER_PHYADDR_SHIFT;
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}
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}
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2021-09-13 18:07:23 +03:00
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static MemTxResult gicv3_its_translation_write(void *opaque, hwaddr offset,
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uint64_t data, unsigned size,
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MemTxAttrs attrs)
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{
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return MEMTX_OK;
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}
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static bool its_writel(GICv3ITSState *s, hwaddr offset,
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uint64_t value, MemTxAttrs attrs)
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{
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bool result = true;
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2021-09-13 18:07:23 +03:00
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int index;
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switch (offset) {
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case GITS_CTLR:
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s->ctlr |= (value & ~(s->ctlr));
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2021-09-13 18:07:23 +03:00
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2021-09-13 18:07:23 +03:00
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if (s->ctlr & ITS_CTLR_ENABLED) {
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extract_table_params(s);
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extract_cmdq_params(s);
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s->creadr = 0;
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}
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break;
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case GITS_CBASER:
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/*
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* IMPDEF choice:- GITS_CBASER register becomes RO if ITS is
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* already enabled
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*/
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if (!(s->ctlr & ITS_CTLR_ENABLED)) {
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s->cbaser = deposit64(s->cbaser, 0, 32, value);
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s->creadr = 0;
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s->cwriter = s->creadr;
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}
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break;
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case GITS_CBASER + 4:
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/*
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* IMPDEF choice:- GITS_CBASER register becomes RO if ITS is
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* already enabled
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*/
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if (!(s->ctlr & ITS_CTLR_ENABLED)) {
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s->cbaser = deposit64(s->cbaser, 32, 32, value);
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s->creadr = 0;
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s->cwriter = s->creadr;
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}
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break;
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case GITS_CWRITER:
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s->cwriter = deposit64(s->cwriter, 0, 32,
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(value & ~R_GITS_CWRITER_RETRY_MASK));
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break;
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case GITS_CWRITER + 4:
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s->cwriter = deposit64(s->cwriter, 32, 32, value);
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break;
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case GITS_CREADR:
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if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) {
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s->creadr = deposit64(s->creadr, 0, 32,
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(value & ~R_GITS_CREADR_STALLED_MASK));
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} else {
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/* RO register, ignore the write */
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: invalid guest write to RO register at offset "
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TARGET_FMT_plx "\n", __func__, offset);
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}
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break;
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case GITS_CREADR + 4:
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if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) {
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s->creadr = deposit64(s->creadr, 32, 32, value);
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} else {
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/* RO register, ignore the write */
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: invalid guest write to RO register at offset "
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TARGET_FMT_plx "\n", __func__, offset);
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}
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break;
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case GITS_BASER ... GITS_BASER + 0x3f:
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/*
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* IMPDEF choice:- GITS_BASERn register becomes RO if ITS is
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* already enabled
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*/
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if (!(s->ctlr & ITS_CTLR_ENABLED)) {
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index = (offset - GITS_BASER) / 8;
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if (offset & 7) {
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value <<= 32;
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value &= ~GITS_BASER_RO_MASK;
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s->baser[index] &= GITS_BASER_RO_MASK | MAKE_64BIT_MASK(0, 32);
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s->baser[index] |= value;
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} else {
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value &= ~GITS_BASER_RO_MASK;
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s->baser[index] &= GITS_BASER_RO_MASK | MAKE_64BIT_MASK(32, 32);
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s->baser[index] |= value;
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}
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}
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break;
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case GITS_IIDR:
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case GITS_IDREGS ... GITS_IDREGS + 0x2f:
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/* RO registers, ignore the write */
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: invalid guest write to RO register at offset "
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TARGET_FMT_plx "\n", __func__, offset);
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break;
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default:
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result = false;
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break;
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}
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2021-09-13 18:07:23 +03:00
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return result;
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}
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static bool its_readl(GICv3ITSState *s, hwaddr offset,
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uint64_t *data, MemTxAttrs attrs)
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{
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bool result = true;
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2021-09-13 18:07:23 +03:00
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int index;
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2021-09-13 18:07:23 +03:00
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2021-09-13 18:07:23 +03:00
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switch (offset) {
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case GITS_CTLR:
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*data = s->ctlr;
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break;
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case GITS_IIDR:
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*data = gicv3_iidr();
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break;
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case GITS_IDREGS ... GITS_IDREGS + 0x2f:
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/* ID registers */
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*data = gicv3_idreg(offset - GITS_IDREGS);
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break;
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case GITS_TYPER:
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*data = extract64(s->typer, 0, 32);
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break;
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case GITS_TYPER + 4:
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*data = extract64(s->typer, 32, 32);
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break;
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case GITS_CBASER:
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*data = extract64(s->cbaser, 0, 32);
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break;
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case GITS_CBASER + 4:
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*data = extract64(s->cbaser, 32, 32);
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break;
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case GITS_CREADR:
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*data = extract64(s->creadr, 0, 32);
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break;
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case GITS_CREADR + 4:
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*data = extract64(s->creadr, 32, 32);
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break;
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case GITS_CWRITER:
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*data = extract64(s->cwriter, 0, 32);
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break;
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case GITS_CWRITER + 4:
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*data = extract64(s->cwriter, 32, 32);
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break;
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case GITS_BASER ... GITS_BASER + 0x3f:
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index = (offset - GITS_BASER) / 8;
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if (offset & 7) {
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*data = extract64(s->baser[index], 32, 32);
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} else {
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*data = extract64(s->baser[index], 0, 32);
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}
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break;
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default:
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result = false;
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break;
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}
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2021-09-13 18:07:23 +03:00
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return result;
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}
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static bool its_writell(GICv3ITSState *s, hwaddr offset,
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uint64_t value, MemTxAttrs attrs)
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{
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bool result = true;
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2021-09-13 18:07:23 +03:00
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int index;
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2021-09-13 18:07:23 +03:00
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2021-09-13 18:07:23 +03:00
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switch (offset) {
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case GITS_BASER ... GITS_BASER + 0x3f:
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/*
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* IMPDEF choice:- GITS_BASERn register becomes RO if ITS is
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|
|
* already enabled
|
|
|
|
*/
|
|
|
|
if (!(s->ctlr & ITS_CTLR_ENABLED)) {
|
|
|
|
index = (offset - GITS_BASER) / 8;
|
|
|
|
s->baser[index] &= GITS_BASER_RO_MASK;
|
|
|
|
s->baser[index] |= (value & ~GITS_BASER_RO_MASK);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case GITS_CBASER:
|
|
|
|
/*
|
|
|
|
* IMPDEF choice:- GITS_CBASER register becomes RO if ITS is
|
|
|
|
* already enabled
|
|
|
|
*/
|
|
|
|
if (!(s->ctlr & ITS_CTLR_ENABLED)) {
|
|
|
|
s->cbaser = value;
|
|
|
|
s->creadr = 0;
|
|
|
|
s->cwriter = s->creadr;
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case GITS_CWRITER:
|
|
|
|
s->cwriter = value & ~R_GITS_CWRITER_RETRY_MASK;
|
|
|
|
break;
|
|
|
|
case GITS_CREADR:
|
|
|
|
if (s->gicv3->gicd_ctlr & GICD_CTLR_DS) {
|
|
|
|
s->creadr = value & ~R_GITS_CREADR_STALLED_MASK;
|
|
|
|
} else {
|
|
|
|
/* RO register, ignore the write */
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: invalid guest write to RO register at offset "
|
|
|
|
TARGET_FMT_plx "\n", __func__, offset);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case GITS_TYPER:
|
|
|
|
/* RO registers, ignore the write */
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: invalid guest write to RO register at offset "
|
|
|
|
TARGET_FMT_plx "\n", __func__, offset);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
result = false;
|
|
|
|
break;
|
|
|
|
}
|
2021-09-13 18:07:23 +03:00
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool its_readll(GICv3ITSState *s, hwaddr offset,
|
|
|
|
uint64_t *data, MemTxAttrs attrs)
|
|
|
|
{
|
|
|
|
bool result = true;
|
2021-09-13 18:07:23 +03:00
|
|
|
int index;
|
2021-09-13 18:07:23 +03:00
|
|
|
|
2021-09-13 18:07:23 +03:00
|
|
|
switch (offset) {
|
|
|
|
case GITS_TYPER:
|
|
|
|
*data = s->typer;
|
|
|
|
break;
|
|
|
|
case GITS_BASER ... GITS_BASER + 0x3f:
|
|
|
|
index = (offset - GITS_BASER) / 8;
|
|
|
|
*data = s->baser[index];
|
|
|
|
break;
|
|
|
|
case GITS_CBASER:
|
|
|
|
*data = s->cbaser;
|
|
|
|
break;
|
|
|
|
case GITS_CREADR:
|
|
|
|
*data = s->creadr;
|
|
|
|
break;
|
|
|
|
case GITS_CWRITER:
|
|
|
|
*data = s->cwriter;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
result = false;
|
|
|
|
break;
|
|
|
|
}
|
2021-09-13 18:07:23 +03:00
|
|
|
return result;
|
|
|
|
}
|
|
|
|
|
|
|
|
static MemTxResult gicv3_its_read(void *opaque, hwaddr offset, uint64_t *data,
|
|
|
|
unsigned size, MemTxAttrs attrs)
|
|
|
|
{
|
|
|
|
GICv3ITSState *s = (GICv3ITSState *)opaque;
|
|
|
|
bool result;
|
|
|
|
|
|
|
|
switch (size) {
|
|
|
|
case 4:
|
|
|
|
result = its_readl(s, offset, data, attrs);
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
result = its_readll(s, offset, data, attrs);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
result = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!result) {
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: invalid guest read at offset " TARGET_FMT_plx
|
|
|
|
"size %u\n", __func__, offset, size);
|
|
|
|
/*
|
|
|
|
* The spec requires that reserved registers are RAZ/WI;
|
|
|
|
* so use false returns from leaf functions as a way to
|
|
|
|
* trigger the guest-error logging but don't return it to
|
|
|
|
* the caller, or we'll cause a spurious guest data abort.
|
|
|
|
*/
|
|
|
|
*data = 0;
|
|
|
|
}
|
|
|
|
return MEMTX_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static MemTxResult gicv3_its_write(void *opaque, hwaddr offset, uint64_t data,
|
|
|
|
unsigned size, MemTxAttrs attrs)
|
|
|
|
{
|
|
|
|
GICv3ITSState *s = (GICv3ITSState *)opaque;
|
|
|
|
bool result;
|
|
|
|
|
|
|
|
switch (size) {
|
|
|
|
case 4:
|
|
|
|
result = its_writel(s, offset, data, attrs);
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
result = its_writell(s, offset, data, attrs);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
result = false;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!result) {
|
|
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
|
|
"%s: invalid guest write at offset " TARGET_FMT_plx
|
|
|
|
"size %u\n", __func__, offset, size);
|
|
|
|
/*
|
|
|
|
* The spec requires that reserved registers are RAZ/WI;
|
|
|
|
* so use false returns from leaf functions as a way to
|
|
|
|
* trigger the guest-error logging but don't return it to
|
|
|
|
* the caller, or we'll cause a spurious guest data abort.
|
|
|
|
*/
|
|
|
|
}
|
|
|
|
return MEMTX_OK;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const MemoryRegionOps gicv3_its_control_ops = {
|
|
|
|
.read_with_attrs = gicv3_its_read,
|
|
|
|
.write_with_attrs = gicv3_its_write,
|
|
|
|
.valid.min_access_size = 4,
|
|
|
|
.valid.max_access_size = 8,
|
|
|
|
.impl.min_access_size = 4,
|
|
|
|
.impl.max_access_size = 8,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const MemoryRegionOps gicv3_its_translation_ops = {
|
|
|
|
.write_with_attrs = gicv3_its_translation_write,
|
|
|
|
.valid.min_access_size = 2,
|
|
|
|
.valid.max_access_size = 4,
|
|
|
|
.impl.min_access_size = 2,
|
|
|
|
.impl.max_access_size = 4,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void gicv3_arm_its_realize(DeviceState *dev, Error **errp)
|
|
|
|
{
|
|
|
|
GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < s->gicv3->num_cpu; i++) {
|
|
|
|
if (!(s->gicv3->cpu[i].gicr_typer & GICR_TYPER_PLPIS)) {
|
|
|
|
error_setg(errp, "Physical LPI not supported by CPU %d", i);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
gicv3_its_init_mmio(s, &gicv3_its_control_ops, &gicv3_its_translation_ops);
|
|
|
|
|
2021-09-13 18:07:23 +03:00
|
|
|
address_space_init(&s->gicv3->dma_as, s->gicv3->dma,
|
|
|
|
"gicv3-its-sysmem");
|
|
|
|
|
2021-09-13 18:07:23 +03:00
|
|
|
/* set the ITS default features supported */
|
|
|
|
s->typer = FIELD_DP64(s->typer, GITS_TYPER, PHYSICAL,
|
|
|
|
GITS_TYPE_PHYSICAL);
|
|
|
|
s->typer = FIELD_DP64(s->typer, GITS_TYPER, ITT_ENTRY_SIZE,
|
|
|
|
ITS_ITT_ENTRY_SIZE - 1);
|
|
|
|
s->typer = FIELD_DP64(s->typer, GITS_TYPER, IDBITS, ITS_IDBITS);
|
|
|
|
s->typer = FIELD_DP64(s->typer, GITS_TYPER, DEVBITS, ITS_DEVBITS);
|
|
|
|
s->typer = FIELD_DP64(s->typer, GITS_TYPER, CIL, 1);
|
|
|
|
s->typer = FIELD_DP64(s->typer, GITS_TYPER, CIDBITS, ITS_CIDBITS);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void gicv3_its_reset(DeviceState *dev)
|
|
|
|
{
|
|
|
|
GICv3ITSState *s = ARM_GICV3_ITS_COMMON(dev);
|
|
|
|
GICv3ITSClass *c = ARM_GICV3_ITS_GET_CLASS(s);
|
|
|
|
|
|
|
|
c->parent_reset(dev);
|
|
|
|
|
|
|
|
/* Quiescent bit reset to 1 */
|
|
|
|
s->ctlr = FIELD_DP32(s->ctlr, GITS_CTLR, QUIESCENT, 1);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* setting GITS_BASER0.Type = 0b001 (Device)
|
|
|
|
* GITS_BASER1.Type = 0b100 (Collection Table)
|
|
|
|
* GITS_BASER<n>.Type,where n = 3 to 7 are 0b00 (Unimplemented)
|
|
|
|
* GITS_BASER<0,1>.Page_Size = 64KB
|
|
|
|
* and default translation table entry size to 16 bytes
|
|
|
|
*/
|
|
|
|
s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, TYPE,
|
|
|
|
GITS_BASER_TYPE_DEVICE);
|
|
|
|
s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, PAGESIZE,
|
|
|
|
GITS_BASER_PAGESIZE_64K);
|
|
|
|
s->baser[0] = FIELD_DP64(s->baser[0], GITS_BASER, ENTRYSIZE,
|
|
|
|
GITS_DTE_SIZE - 1);
|
|
|
|
|
|
|
|
s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, TYPE,
|
|
|
|
GITS_BASER_TYPE_COLLECTION);
|
|
|
|
s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, PAGESIZE,
|
|
|
|
GITS_BASER_PAGESIZE_64K);
|
|
|
|
s->baser[1] = FIELD_DP64(s->baser[1], GITS_BASER, ENTRYSIZE,
|
|
|
|
GITS_CTE_SIZE - 1);
|
|
|
|
}
|
|
|
|
|
2021-09-13 18:07:23 +03:00
|
|
|
static void gicv3_its_post_load(GICv3ITSState *s)
|
|
|
|
{
|
|
|
|
if (s->ctlr & ITS_CTLR_ENABLED) {
|
|
|
|
extract_table_params(s);
|
|
|
|
extract_cmdq_params(s);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-09-13 18:07:23 +03:00
|
|
|
static Property gicv3_its_props[] = {
|
|
|
|
DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "arm-gicv3",
|
|
|
|
GICv3State *),
|
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
|
|
|
static void gicv3_its_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
GICv3ITSClass *ic = ARM_GICV3_ITS_CLASS(klass);
|
2021-09-13 18:07:23 +03:00
|
|
|
GICv3ITSCommonClass *icc = ARM_GICV3_ITS_COMMON_CLASS(klass);
|
2021-09-13 18:07:23 +03:00
|
|
|
|
|
|
|
dc->realize = gicv3_arm_its_realize;
|
|
|
|
device_class_set_props(dc, gicv3_its_props);
|
|
|
|
device_class_set_parent_reset(dc, gicv3_its_reset, &ic->parent_reset);
|
2021-09-13 18:07:23 +03:00
|
|
|
icc->post_load = gicv3_its_post_load;
|
2021-09-13 18:07:23 +03:00
|
|
|
}
|
|
|
|
|
|
|
|
static const TypeInfo gicv3_its_info = {
|
|
|
|
.name = TYPE_ARM_GICV3_ITS,
|
|
|
|
.parent = TYPE_ARM_GICV3_ITS_COMMON,
|
|
|
|
.instance_size = sizeof(GICv3ITSState),
|
|
|
|
.class_init = gicv3_its_class_init,
|
|
|
|
.class_size = sizeof(GICv3ITSClass),
|
|
|
|
};
|
|
|
|
|
|
|
|
static void gicv3_its_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&gicv3_its_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(gicv3_its_register_types)
|