2009-08-20 17:22:21 +04:00
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/*
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* QEMU IDE Emulation: MacIO support.
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*
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* Copyright (c) 2003 Fabrice Bellard
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* Copyright (c) 2006 Openedhand Ltd.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2013-01-24 03:03:54 +04:00
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#include "hw/hw.h"
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#include "hw/ppc/mac.h"
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2013-02-05 20:06:20 +04:00
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#include "hw/ppc/mac_dbdma.h"
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2012-12-17 21:19:44 +04:00
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#include "block/block.h"
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2012-12-17 21:20:04 +04:00
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#include "sysemu/dma.h"
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2009-08-20 17:22:26 +04:00
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#include <hw/ide/internal.h>
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2009-08-20 17:22:21 +04:00
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2013-06-30 03:23:45 +04:00
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/* debug MACIO */
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// #define DEBUG_MACIO
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#ifdef DEBUG_MACIO
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static const int debug_macio = 1;
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#else
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static const int debug_macio = 0;
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#endif
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#define MACIO_DPRINTF(fmt, ...) do { \
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if (debug_macio) { \
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printf(fmt , ## __VA_ARGS__); \
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} \
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} while (0)
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2009-08-20 17:22:21 +04:00
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/***********************************************************/
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/* MacIO based PowerPC IDE */
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2010-03-29 23:23:57 +04:00
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#define MACIO_PAGE_SIZE 4096
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2009-08-20 17:22:21 +04:00
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static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
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{
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DBDMA_io *io = opaque;
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MACIOIDEState *m = io->opaque;
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IDEState *s = idebus_active_if(&m->bus);
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2013-06-28 15:30:01 +04:00
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int unaligned;
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2009-08-20 17:22:21 +04:00
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if (ret < 0) {
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m->aiocb = NULL;
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qemu_sglist_destroy(&s->sg);
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ide_atapi_io_error(s, ret);
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2013-06-28 15:30:01 +04:00
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io->remainder_len = 0;
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2011-08-25 10:26:01 +04:00
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goto done;
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2009-08-20 17:22:21 +04:00
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}
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2013-06-30 04:54:35 +04:00
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if (!m->dma_active) {
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MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
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s->nsector, io->len, s->status);
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/* data not ready yet, wait for the channel to get restarted */
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io->processing = false;
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return;
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}
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2013-06-30 03:23:45 +04:00
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MACIO_DPRINTF("io_buffer_size = %#x\n", s->io_buffer_size);
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2009-08-20 17:22:21 +04:00
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if (s->io_buffer_size > 0) {
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m->aiocb = NULL;
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qemu_sglist_destroy(&s->sg);
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s->packet_transfer_size -= s->io_buffer_size;
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s->io_buffer_index += s->io_buffer_size;
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2013-06-30 03:43:17 +04:00
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s->lba += s->io_buffer_index >> 11;
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2009-08-20 17:22:21 +04:00
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s->io_buffer_index &= 0x7ff;
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}
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2013-06-30 17:29:13 +04:00
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s->io_buffer_size = MIN(io->len, s->packet_transfer_size);
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2013-06-28 15:30:01 +04:00
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MACIO_DPRINTF("remainder: %d io->len: %d size: %d\n", io->remainder_len,
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io->len, s->packet_transfer_size);
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if (io->remainder_len && io->len) {
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/* guest wants the rest of its previous transfer */
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int remainder_len = MIN(io->remainder_len, io->len);
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MACIO_DPRINTF("copying remainder %d bytes\n", remainder_len);
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cpu_physical_memory_write(io->addr, io->remainder + 0x200 -
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remainder_len, remainder_len);
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io->addr += remainder_len;
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io->len -= remainder_len;
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s->io_buffer_size = remainder_len;
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io->remainder_len -= remainder_len;
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/* treat remainder as individual transfer, start again */
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qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
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&address_space_memory);
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pmac_ide_atapi_transfer_cb(opaque, 0);
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return;
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}
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if (!s->packet_transfer_size) {
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2013-06-30 03:23:45 +04:00
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MACIO_DPRINTF("end of transfer\n");
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2009-08-20 17:22:21 +04:00
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ide_atapi_cmd_ok(s);
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2013-06-30 04:54:35 +04:00
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m->dma_active = false;
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2013-06-30 03:23:45 +04:00
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}
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2009-08-20 17:22:21 +04:00
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if (io->len == 0) {
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2013-06-30 03:23:45 +04:00
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MACIO_DPRINTF("end of DMA\n");
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2011-08-25 10:26:01 +04:00
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goto done;
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2009-08-20 17:22:21 +04:00
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}
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/* launch next transfer */
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2013-06-28 15:30:01 +04:00
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/* handle unaligned accesses first, get them over with and only do the
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remaining bulk transfer using our async DMA helpers */
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unaligned = io->len & 0x1ff;
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if (unaligned) {
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int sector_num = (s->lba << 2) + (s->io_buffer_index >> 9);
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int nsector = io->len >> 9;
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2013-06-30 03:23:45 +04:00
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2013-07-12 20:48:39 +04:00
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MACIO_DPRINTF("precopying unaligned %d bytes to %#" HWADDR_PRIx "\n",
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2013-06-28 15:30:01 +04:00
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unaligned, io->addr + io->len - unaligned);
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bdrv_read(s->bs, sector_num + nsector, io->remainder, 1);
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cpu_physical_memory_write(io->addr + io->len - unaligned,
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io->remainder, unaligned);
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io->len -= unaligned;
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}
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MACIO_DPRINTF("io->len = %#x\n", io->len);
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2009-08-20 17:22:21 +04:00
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2013-06-03 16:17:19 +04:00
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qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
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2013-04-10 20:15:49 +04:00
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&address_space_memory);
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2009-08-20 17:22:21 +04:00
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qemu_sglist_add(&s->sg, io->addr, io->len);
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2013-06-28 15:30:01 +04:00
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io->addr += s->io_buffer_size;
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io->remainder_len = MIN(s->packet_transfer_size - s->io_buffer_size,
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(0x200 - unaligned) & 0x1ff);
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MACIO_DPRINTF("set remainder to: %d\n", io->remainder_len);
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/* We would read no data from the block layer, thus not get a callback.
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Just fake completion manually. */
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if (!io->len) {
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pmac_ide_atapi_transfer_cb(opaque, 0);
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return;
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}
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2009-08-20 17:22:21 +04:00
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io->len = 0;
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2013-06-30 03:23:45 +04:00
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MACIO_DPRINTF("sector_num=%d size=%d, cmd_cmd=%d\n",
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(s->lba << 2) + (s->io_buffer_index >> 9),
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s->packet_transfer_size, s->dma_cmd);
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2009-08-20 17:22:21 +04:00
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m->aiocb = dma_bdrv_read(s->bs, &s->sg,
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(int64_t)(s->lba << 2) + (s->io_buffer_index >> 9),
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pmac_ide_atapi_transfer_cb, io);
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2011-08-25 10:26:01 +04:00
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return;
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done:
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2013-06-30 03:23:45 +04:00
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MACIO_DPRINTF("done DMA\n");
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2014-09-05 17:46:18 +04:00
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block_acct_done(bdrv_get_stats(s->bs), &s->acct);
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2011-08-25 10:26:01 +04:00
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io->dma_end(opaque);
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2009-08-20 17:22:21 +04:00
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}
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static void pmac_ide_transfer_cb(void *opaque, int ret)
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{
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DBDMA_io *io = opaque;
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MACIOIDEState *m = io->opaque;
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IDEState *s = idebus_active_if(&m->bus);
|
2013-06-28 15:30:01 +04:00
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int n = 0;
|
2009-08-20 17:22:21 +04:00
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int64_t sector_num;
|
2013-06-28 15:30:01 +04:00
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int unaligned;
|
2009-08-20 17:22:21 +04:00
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if (ret < 0) {
|
2013-06-30 03:23:45 +04:00
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MACIO_DPRINTF("DMA error\n");
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2009-08-20 17:22:21 +04:00
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m->aiocb = NULL;
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qemu_sglist_destroy(&s->sg);
|
2013-06-30 03:43:17 +04:00
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ide_dma_error(s);
|
2013-06-28 15:30:01 +04:00
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io->remainder_len = 0;
|
2011-08-25 10:26:01 +04:00
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goto done;
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2009-08-20 17:22:21 +04:00
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}
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|
2014-05-26 12:27:58 +04:00
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if (--io->requests) {
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/* More requests still in flight */
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return;
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}
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|
2013-06-30 04:54:35 +04:00
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if (!m->dma_active) {
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MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
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s->nsector, io->len, s->status);
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/* data not ready yet, wait for the channel to get restarted */
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io->processing = false;
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return;
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}
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|
2009-08-20 17:22:21 +04:00
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sector_num = ide_get_sector(s);
|
2013-06-30 03:23:45 +04:00
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MACIO_DPRINTF("io_buffer_size = %#x\n", s->io_buffer_size);
|
2009-08-20 17:22:21 +04:00
|
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|
if (s->io_buffer_size > 0) {
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m->aiocb = NULL;
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qemu_sglist_destroy(&s->sg);
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n = (s->io_buffer_size + 0x1ff) >> 9;
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|
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sector_num += n;
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ide_set_sector(s, sector_num);
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s->nsector -= n;
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}
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|
|
2014-05-26 12:27:58 +04:00
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|
|
if (io->finish_remain_read) {
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|
|
|
/* Finish a stale read from the last iteration */
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|
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io->finish_remain_read = false;
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cpu_physical_memory_write(io->finish_addr, io->remainder,
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io->finish_len);
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}
|
|
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|
|
2013-07-12 20:48:39 +04:00
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MACIO_DPRINTF("remainder: %d io->len: %d nsector: %d "
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"sector_num: %" PRId64 "\n",
|
2013-06-28 15:30:01 +04:00
|
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io->remainder_len, io->len, s->nsector, sector_num);
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|
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if (io->remainder_len && io->len) {
|
|
|
|
/* guest wants the rest of its previous transfer */
|
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|
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int remainder_len = MIN(io->remainder_len, io->len);
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|
|
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uint8_t *p = &io->remainder[0x200 - remainder_len];
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|
|
|
|
2013-07-12 20:48:39 +04:00
|
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MACIO_DPRINTF("copying remainder %d bytes at %#" HWADDR_PRIx "\n",
|
2013-06-28 15:30:01 +04:00
|
|
|
remainder_len, io->addr);
|
|
|
|
|
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|
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switch (s->dma_cmd) {
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case IDE_DMA_READ:
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cpu_physical_memory_write(io->addr, p, remainder_len);
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break;
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case IDE_DMA_WRITE:
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cpu_physical_memory_read(io->addr, p, remainder_len);
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|
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break;
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|
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case IDE_DMA_TRIM:
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|
|
break;
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|
|
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}
|
|
|
|
io->addr += remainder_len;
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|
|
|
io->len -= remainder_len;
|
|
|
|
io->remainder_len -= remainder_len;
|
2014-05-26 12:27:58 +04:00
|
|
|
|
|
|
|
if (s->dma_cmd == IDE_DMA_WRITE && !io->remainder_len) {
|
|
|
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io->requests++;
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|
|
qemu_iovec_reset(&io->iov);
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|
|
qemu_iovec_add(&io->iov, io->remainder, 0x200);
|
|
|
|
|
|
|
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m->aiocb = bdrv_aio_writev(s->bs, sector_num - 1, &io->iov, 1,
|
|
|
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pmac_ide_transfer_cb, io);
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|
|
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}
|
2013-06-28 15:30:01 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
if (s->nsector == 0 && !io->remainder_len) {
|
2013-06-30 03:23:45 +04:00
|
|
|
MACIO_DPRINTF("end of transfer\n");
|
2009-08-20 17:22:21 +04:00
|
|
|
s->status = READY_STAT | SEEK_STAT;
|
2009-08-28 18:37:42 +04:00
|
|
|
ide_set_irq(s->bus);
|
2013-06-30 04:54:35 +04:00
|
|
|
m->dma_active = false;
|
2009-08-20 17:22:21 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
if (io->len == 0) {
|
2013-06-30 03:23:45 +04:00
|
|
|
MACIO_DPRINTF("end of DMA\n");
|
2011-08-25 10:26:01 +04:00
|
|
|
goto done;
|
2009-08-20 17:22:21 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* launch next transfer */
|
|
|
|
|
|
|
|
s->io_buffer_index = 0;
|
2013-06-30 17:29:13 +04:00
|
|
|
s->io_buffer_size = MIN(io->len, s->nsector * 512);
|
2009-08-20 17:22:21 +04:00
|
|
|
|
2013-06-28 15:30:01 +04:00
|
|
|
/* handle unaligned accesses first, get them over with and only do the
|
|
|
|
remaining bulk transfer using our async DMA helpers */
|
|
|
|
unaligned = io->len & 0x1ff;
|
|
|
|
if (unaligned) {
|
|
|
|
int nsector = io->len >> 9;
|
|
|
|
|
2013-07-12 20:48:39 +04:00
|
|
|
MACIO_DPRINTF("precopying unaligned %d bytes to %#" HWADDR_PRIx "\n",
|
2013-06-28 15:30:01 +04:00
|
|
|
unaligned, io->addr + io->len - unaligned);
|
|
|
|
|
|
|
|
switch (s->dma_cmd) {
|
|
|
|
case IDE_DMA_READ:
|
2014-05-26 12:27:58 +04:00
|
|
|
io->requests++;
|
|
|
|
io->finish_addr = io->addr + io->len - unaligned;
|
|
|
|
io->finish_len = unaligned;
|
|
|
|
io->finish_remain_read = true;
|
|
|
|
qemu_iovec_reset(&io->iov);
|
|
|
|
qemu_iovec_add(&io->iov, io->remainder, 0x200);
|
|
|
|
|
|
|
|
m->aiocb = bdrv_aio_readv(s->bs, sector_num + nsector, &io->iov, 1,
|
|
|
|
pmac_ide_transfer_cb, io);
|
2013-06-28 15:30:01 +04:00
|
|
|
break;
|
|
|
|
case IDE_DMA_WRITE:
|
|
|
|
/* cache the contents in our io struct */
|
|
|
|
cpu_physical_memory_read(io->addr + io->len - unaligned,
|
2014-05-26 12:27:58 +04:00
|
|
|
io->remainder + io->remainder_len,
|
|
|
|
unaligned);
|
2013-06-28 15:30:01 +04:00
|
|
|
break;
|
|
|
|
case IDE_DMA_TRIM:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-06-30 03:23:45 +04:00
|
|
|
MACIO_DPRINTF("io->len = %#x\n", io->len);
|
|
|
|
|
2013-06-03 16:17:19 +04:00
|
|
|
qemu_sglist_init(&s->sg, DEVICE(m), io->len / MACIO_PAGE_SIZE + 1,
|
2013-04-10 20:15:49 +04:00
|
|
|
&address_space_memory);
|
2009-08-20 17:22:21 +04:00
|
|
|
qemu_sglist_add(&s->sg, io->addr, io->len);
|
2013-06-28 15:30:01 +04:00
|
|
|
io->addr += io->len + unaligned;
|
|
|
|
io->remainder_len = (0x200 - unaligned) & 0x1ff;
|
|
|
|
MACIO_DPRINTF("set remainder to: %d\n", io->remainder_len);
|
|
|
|
|
2014-05-26 12:27:58 +04:00
|
|
|
/* Only subsector reads happening */
|
2013-06-28 15:30:01 +04:00
|
|
|
if (!io->len) {
|
2014-05-26 12:27:58 +04:00
|
|
|
if (!io->requests) {
|
|
|
|
io->requests++;
|
|
|
|
pmac_ide_transfer_cb(opaque, ret);
|
|
|
|
}
|
2013-06-28 15:30:01 +04:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2009-08-20 17:22:21 +04:00
|
|
|
io->len = 0;
|
|
|
|
|
2013-06-30 03:23:45 +04:00
|
|
|
MACIO_DPRINTF("sector_num=%" PRId64 " n=%d, nsector=%d, cmd_cmd=%d\n",
|
|
|
|
sector_num, n, s->nsector, s->dma_cmd);
|
|
|
|
|
2011-05-19 12:58:09 +04:00
|
|
|
switch (s->dma_cmd) {
|
|
|
|
case IDE_DMA_READ:
|
2009-08-20 17:22:21 +04:00
|
|
|
m->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
|
2013-06-30 03:43:17 +04:00
|
|
|
pmac_ide_transfer_cb, io);
|
2011-05-19 12:58:09 +04:00
|
|
|
break;
|
|
|
|
case IDE_DMA_WRITE:
|
2009-08-20 17:22:21 +04:00
|
|
|
m->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
|
2013-06-30 03:43:17 +04:00
|
|
|
pmac_ide_transfer_cb, io);
|
2011-05-19 12:58:09 +04:00
|
|
|
break;
|
2011-05-19 12:58:19 +04:00
|
|
|
case IDE_DMA_TRIM:
|
|
|
|
m->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
|
2013-05-19 15:22:11 +04:00
|
|
|
ide_issue_trim, pmac_ide_transfer_cb, io,
|
2012-03-27 06:42:23 +04:00
|
|
|
DMA_DIRECTION_TO_DEVICE);
|
2011-05-19 12:58:19 +04:00
|
|
|
break;
|
2011-05-19 12:58:09 +04:00
|
|
|
}
|
2014-05-26 12:27:58 +04:00
|
|
|
|
|
|
|
io->requests++;
|
2011-08-25 10:26:01 +04:00
|
|
|
return;
|
2011-11-14 20:50:53 +04:00
|
|
|
|
2011-08-25 10:26:01 +04:00
|
|
|
done:
|
|
|
|
if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
|
2014-09-05 17:46:18 +04:00
|
|
|
block_acct_done(bdrv_get_stats(s->bs), &s->acct);
|
2011-08-25 10:26:01 +04:00
|
|
|
}
|
|
|
|
io->dma_end(io);
|
2009-08-20 17:22:21 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void pmac_ide_transfer(DBDMA_io *io)
|
|
|
|
{
|
|
|
|
MACIOIDEState *m = io->opaque;
|
|
|
|
IDEState *s = idebus_active_if(&m->bus);
|
|
|
|
|
2013-06-30 03:23:45 +04:00
|
|
|
MACIO_DPRINTF("\n");
|
|
|
|
|
2009-08-20 17:22:21 +04:00
|
|
|
s->io_buffer_size = 0;
|
2010-05-28 15:32:45 +04:00
|
|
|
if (s->drive_kind == IDE_CD) {
|
2014-05-18 16:20:55 +04:00
|
|
|
|
|
|
|
/* Handle non-block ATAPI DMA transfers */
|
|
|
|
if (s->lba == -1) {
|
|
|
|
s->io_buffer_size = MIN(io->len, s->packet_transfer_size);
|
2014-09-05 17:46:18 +04:00
|
|
|
block_acct_start(bdrv_get_stats(s->bs), &s->acct, s->io_buffer_size,
|
|
|
|
BLOCK_ACCT_READ);
|
2014-05-18 16:20:55 +04:00
|
|
|
MACIO_DPRINTF("non-block ATAPI DMA transfer size: %d\n",
|
|
|
|
s->io_buffer_size);
|
|
|
|
|
|
|
|
/* Copy ATAPI buffer directly to RAM and finish */
|
|
|
|
cpu_physical_memory_write(io->addr, s->io_buffer,
|
|
|
|
s->io_buffer_size);
|
|
|
|
ide_atapi_cmd_ok(s);
|
|
|
|
m->dma_active = false;
|
|
|
|
|
|
|
|
MACIO_DPRINTF("end of non-block ATAPI DMA transfer\n");
|
2014-09-05 17:46:18 +04:00
|
|
|
block_acct_done(bdrv_get_stats(s->bs), &s->acct);
|
2014-05-18 16:20:55 +04:00
|
|
|
io->dma_end(io);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2014-09-05 17:46:18 +04:00
|
|
|
block_acct_start(bdrv_get_stats(s->bs), &s->acct, io->len,
|
|
|
|
BLOCK_ACCT_READ);
|
2009-08-20 17:22:21 +04:00
|
|
|
pmac_ide_atapi_transfer_cb(io, 0);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2011-08-25 10:26:01 +04:00
|
|
|
switch (s->dma_cmd) {
|
|
|
|
case IDE_DMA_READ:
|
2014-09-05 17:46:18 +04:00
|
|
|
block_acct_start(bdrv_get_stats(s->bs), &s->acct, io->len,
|
|
|
|
BLOCK_ACCT_READ);
|
2011-08-25 10:26:01 +04:00
|
|
|
break;
|
|
|
|
case IDE_DMA_WRITE:
|
2014-09-05 17:46:18 +04:00
|
|
|
block_acct_start(bdrv_get_stats(s->bs), &s->acct, io->len,
|
|
|
|
BLOCK_ACCT_WRITE);
|
2011-08-25 10:26:01 +04:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2014-05-26 12:27:58 +04:00
|
|
|
io->requests++;
|
2009-08-20 17:22:21 +04:00
|
|
|
pmac_ide_transfer_cb(io, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pmac_ide_flush(DBDMA_io *io)
|
|
|
|
{
|
|
|
|
MACIOIDEState *m = io->opaque;
|
|
|
|
|
2011-11-30 16:23:43 +04:00
|
|
|
if (m->aiocb) {
|
|
|
|
bdrv_drain_all();
|
|
|
|
}
|
2009-08-20 17:22:21 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* PowerMac IDE memory IO */
|
|
|
|
static void pmac_ide_writeb (void *opaque,
|
2012-10-23 14:30:10 +04:00
|
|
|
hwaddr addr, uint32_t val)
|
2009-08-20 17:22:21 +04:00
|
|
|
{
|
|
|
|
MACIOIDEState *d = opaque;
|
|
|
|
|
|
|
|
addr = (addr & 0xFFF) >> 4;
|
|
|
|
switch (addr) {
|
|
|
|
case 1 ... 7:
|
|
|
|
ide_ioport_write(&d->bus, addr, val);
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
case 22:
|
|
|
|
ide_cmd_write(&d->bus, 0, val);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-23 14:30:10 +04:00
|
|
|
static uint32_t pmac_ide_readb (void *opaque,hwaddr addr)
|
2009-08-20 17:22:21 +04:00
|
|
|
{
|
|
|
|
uint8_t retval;
|
|
|
|
MACIOIDEState *d = opaque;
|
|
|
|
|
|
|
|
addr = (addr & 0xFFF) >> 4;
|
|
|
|
switch (addr) {
|
|
|
|
case 1 ... 7:
|
|
|
|
retval = ide_ioport_read(&d->bus, addr);
|
|
|
|
break;
|
|
|
|
case 8:
|
|
|
|
case 22:
|
|
|
|
retval = ide_status_read(&d->bus, 0);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
retval = 0xFF;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pmac_ide_writew (void *opaque,
|
2012-10-23 14:30:10 +04:00
|
|
|
hwaddr addr, uint32_t val)
|
2009-08-20 17:22:21 +04:00
|
|
|
{
|
|
|
|
MACIOIDEState *d = opaque;
|
|
|
|
|
|
|
|
addr = (addr & 0xFFF) >> 4;
|
|
|
|
val = bswap16(val);
|
|
|
|
if (addr == 0) {
|
|
|
|
ide_data_writew(&d->bus, 0, val);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-23 14:30:10 +04:00
|
|
|
static uint32_t pmac_ide_readw (void *opaque,hwaddr addr)
|
2009-08-20 17:22:21 +04:00
|
|
|
{
|
|
|
|
uint16_t retval;
|
|
|
|
MACIOIDEState *d = opaque;
|
|
|
|
|
|
|
|
addr = (addr & 0xFFF) >> 4;
|
|
|
|
if (addr == 0) {
|
|
|
|
retval = ide_data_readw(&d->bus, 0);
|
|
|
|
} else {
|
|
|
|
retval = 0xFFFF;
|
|
|
|
}
|
|
|
|
retval = bswap16(retval);
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pmac_ide_writel (void *opaque,
|
2012-10-23 14:30:10 +04:00
|
|
|
hwaddr addr, uint32_t val)
|
2009-08-20 17:22:21 +04:00
|
|
|
{
|
|
|
|
MACIOIDEState *d = opaque;
|
|
|
|
|
|
|
|
addr = (addr & 0xFFF) >> 4;
|
|
|
|
val = bswap32(val);
|
|
|
|
if (addr == 0) {
|
|
|
|
ide_data_writel(&d->bus, 0, val);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-23 14:30:10 +04:00
|
|
|
static uint32_t pmac_ide_readl (void *opaque,hwaddr addr)
|
2009-08-20 17:22:21 +04:00
|
|
|
{
|
|
|
|
uint32_t retval;
|
|
|
|
MACIOIDEState *d = opaque;
|
|
|
|
|
|
|
|
addr = (addr & 0xFFF) >> 4;
|
|
|
|
if (addr == 0) {
|
|
|
|
retval = ide_data_readl(&d->bus, 0);
|
|
|
|
} else {
|
|
|
|
retval = 0xFFFFFFFF;
|
|
|
|
}
|
|
|
|
retval = bswap32(retval);
|
|
|
|
return retval;
|
|
|
|
}
|
|
|
|
|
2012-02-05 14:19:07 +04:00
|
|
|
static const MemoryRegionOps pmac_ide_ops = {
|
2011-08-08 17:09:17 +04:00
|
|
|
.old_mmio = {
|
|
|
|
.write = {
|
|
|
|
pmac_ide_writeb,
|
|
|
|
pmac_ide_writew,
|
|
|
|
pmac_ide_writel,
|
|
|
|
},
|
|
|
|
.read = {
|
|
|
|
pmac_ide_readb,
|
|
|
|
pmac_ide_readw,
|
|
|
|
pmac_ide_readl,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2009-08-20 17:22:21 +04:00
|
|
|
};
|
|
|
|
|
2009-10-07 21:04:46 +04:00
|
|
|
static const VMStateDescription vmstate_pmac = {
|
|
|
|
.name = "ide",
|
|
|
|
.version_id = 3,
|
|
|
|
.minimum_version_id = 0,
|
2014-04-16 18:01:33 +04:00
|
|
|
.fields = (VMStateField[]) {
|
2009-10-07 21:04:46 +04:00
|
|
|
VMSTATE_IDE_BUS(bus, MACIOIDEState),
|
|
|
|
VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
2009-08-20 17:22:21 +04:00
|
|
|
}
|
2009-10-07 21:04:46 +04:00
|
|
|
};
|
2009-08-20 17:22:21 +04:00
|
|
|
|
2013-01-24 03:04:01 +04:00
|
|
|
static void macio_ide_reset(DeviceState *dev)
|
2009-08-20 17:22:21 +04:00
|
|
|
{
|
2013-01-24 03:04:01 +04:00
|
|
|
MACIOIDEState *d = MACIO_IDE(dev);
|
2009-08-20 17:22:21 +04:00
|
|
|
|
2009-11-07 17:13:05 +03:00
|
|
|
ide_bus_reset(&d->bus);
|
2009-08-20 17:22:21 +04:00
|
|
|
}
|
|
|
|
|
2013-06-30 04:36:14 +04:00
|
|
|
static int ide_nop_int(IDEDMA *dma, int x)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ide_nop_restart(void *opaque, int x, RunState y)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static void ide_dbdma_start(IDEDMA *dma, IDEState *s,
|
2014-10-07 15:59:15 +04:00
|
|
|
BlockCompletionFunc *cb)
|
2013-06-30 04:36:14 +04:00
|
|
|
{
|
|
|
|
MACIOIDEState *m = container_of(dma, MACIOIDEState, dma);
|
|
|
|
|
|
|
|
MACIO_DPRINTF("\n");
|
2013-06-30 04:54:35 +04:00
|
|
|
m->dma_active = true;
|
2013-06-30 04:36:14 +04:00
|
|
|
DBDMA_kick(m->dbdma);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const IDEDMAOps dbdma_ops = {
|
|
|
|
.start_dma = ide_dbdma_start,
|
|
|
|
.prepare_buf = ide_nop_int,
|
|
|
|
.rw_buf = ide_nop_int,
|
|
|
|
.set_unit = ide_nop_int,
|
|
|
|
.restart_cb = ide_nop_restart,
|
|
|
|
};
|
|
|
|
|
2013-01-24 03:04:01 +04:00
|
|
|
static void macio_ide_realizefn(DeviceState *dev, Error **errp)
|
2009-08-20 17:22:21 +04:00
|
|
|
{
|
2013-01-24 03:04:01 +04:00
|
|
|
MACIOIDEState *s = MACIO_IDE(dev);
|
|
|
|
|
|
|
|
ide_init2(&s->bus, s->irq);
|
2013-06-30 04:36:14 +04:00
|
|
|
|
|
|
|
/* Register DMA callbacks */
|
|
|
|
s->dma.ops = &dbdma_ops;
|
|
|
|
s->bus.dma = &s->dma;
|
2013-01-24 03:04:01 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
static void macio_ide_initfn(Object *obj)
|
|
|
|
{
|
|
|
|
SysBusDevice *d = SYS_BUS_DEVICE(obj);
|
|
|
|
MACIOIDEState *s = MACIO_IDE(obj);
|
|
|
|
|
2013-08-23 22:18:50 +04:00
|
|
|
ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
|
2013-06-07 05:25:08 +04:00
|
|
|
memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
|
2013-01-24 03:04:01 +04:00
|
|
|
sysbus_init_mmio(d, &s->mem);
|
|
|
|
sysbus_init_irq(d, &s->irq);
|
|
|
|
sysbus_init_irq(d, &s->dma_irq);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void macio_ide_class_init(ObjectClass *oc, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
|
|
|
|
dc->realize = macio_ide_realizefn;
|
|
|
|
dc->reset = macio_ide_reset;
|
|
|
|
dc->vmsd = &vmstate_pmac;
|
|
|
|
}
|
2009-08-20 17:22:21 +04:00
|
|
|
|
2013-01-24 03:04:01 +04:00
|
|
|
static const TypeInfo macio_ide_type_info = {
|
|
|
|
.name = TYPE_MACIO_IDE,
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|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
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|
|
|
.instance_size = sizeof(MACIOIDEState),
|
|
|
|
.instance_init = macio_ide_initfn,
|
|
|
|
.class_init = macio_ide_class_init,
|
|
|
|
};
|
2009-08-20 17:22:21 +04:00
|
|
|
|
2013-01-24 03:04:01 +04:00
|
|
|
static void macio_ide_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&macio_ide_type_info);
|
|
|
|
}
|
2009-08-20 17:22:21 +04:00
|
|
|
|
2013-06-24 23:40:50 +04:00
|
|
|
/* hd_table must contain 2 block drivers */
|
2013-01-24 03:04:01 +04:00
|
|
|
void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)
|
|
|
|
{
|
|
|
|
int i;
|
2009-08-20 17:22:21 +04:00
|
|
|
|
2013-01-24 03:04:01 +04:00
|
|
|
for (i = 0; i < 2; i++) {
|
|
|
|
if (hd_table[i]) {
|
|
|
|
ide_create_drive(&s->bus, i, hd_table[i]);
|
|
|
|
}
|
|
|
|
}
|
2009-08-20 17:22:21 +04:00
|
|
|
}
|
2013-01-24 03:04:01 +04:00
|
|
|
|
|
|
|
void macio_ide_register_dma(MACIOIDEState *s, void *dbdma, int channel)
|
|
|
|
{
|
2013-06-30 04:36:14 +04:00
|
|
|
s->dbdma = dbdma;
|
2013-01-24 03:04:01 +04:00
|
|
|
DBDMA_register_channel(dbdma, channel, s->dma_irq,
|
|
|
|
pmac_ide_transfer, pmac_ide_flush, s);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(macio_ide_register_types)
|