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mirror_qemu/target/arm/t32.decode

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target/arm: Add stubs for aa32 decodetree Add the infrastructure that will become the new decoder. No instructions adjusted so far. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 22:29:52 +03:00
# Thumb2 instructions
#
# Copyright (c) 2019 Linaro, Ltd
#
# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2 of the License, or (at your option) any later version.
#
# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# Lesser General Public License for more details.
#
# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, see <http://www.gnu.org/licenses/>.
#
# This file is processed by scripts/decodetree.py
#
target/arm: Convert Data Processing (register) Convert the register shifted by immediate form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the reg-shifted-reg and immediate forms. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 22:29:53 +03:00
&s_rrr_shi !extern s rd rn rm shim shty
target/arm: Convert Data Processing (reg-shifted-reg) Convert the register shifted by register form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the immediate form. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 22:29:54 +03:00
&s_rrr_shr !extern s rn rd rm rs shty
target/arm: Convert Data Processing (immediate) Convert the modified immediate form of the data processing insns. For A32, we can finally remove any code that was intertwined with the register and register-shifted-register forms. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 22:29:55 +03:00
&s_rri_rot !extern s rn rd imm rot
target/arm: Convert Data Processing (register) Convert the register shifted by immediate form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the reg-shifted-reg and immediate forms. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 22:29:53 +03:00
# Data-processing (register)
%imm5_12_6 12:3 6:2
@s_rrr_shi ....... .... s:1 rn:4 .... rd:4 .. shty:2 rm:4 \
&s_rrr_shi shim=%imm5_12_6
@s_rxr_shi ....... .... s:1 .... .... rd:4 .. shty:2 rm:4 \
&s_rrr_shi shim=%imm5_12_6 rn=0
@S_xrr_shi ....... .... . rn:4 .... .... .. shty:2 rm:4 \
&s_rrr_shi shim=%imm5_12_6 s=1 rd=0
{
TST_xrri 1110101 0000 1 .... 0 ... 1111 .... .... @S_xrr_shi
AND_rrri 1110101 0000 . .... 0 ... .... .... .... @s_rrr_shi
}
BIC_rrri 1110101 0001 . .... 0 ... .... .... .... @s_rrr_shi
{
MOV_rxri 1110101 0010 . 1111 0 ... .... .... .... @s_rxr_shi
ORR_rrri 1110101 0010 . .... 0 ... .... .... .... @s_rrr_shi
}
{
MVN_rxri 1110101 0011 . 1111 0 ... .... .... .... @s_rxr_shi
ORN_rrri 1110101 0011 . .... 0 ... .... .... .... @s_rrr_shi
}
{
TEQ_xrri 1110101 0100 1 .... 0 ... 1111 .... .... @S_xrr_shi
EOR_rrri 1110101 0100 . .... 0 ... .... .... .... @s_rrr_shi
}
# PKHBT, PKHTB at opc1 = 0110
{
CMN_xrri 1110101 1000 1 .... 0 ... 1111 .... .... @S_xrr_shi
ADD_rrri 1110101 1000 . .... 0 ... .... .... .... @s_rrr_shi
}
ADC_rrri 1110101 1010 . .... 0 ... .... .... .... @s_rrr_shi
SBC_rrri 1110101 1011 . .... 0 ... .... .... .... @s_rrr_shi
{
CMP_xrri 1110101 1101 1 .... 0 ... 1111 .... .... @S_xrr_shi
SUB_rrri 1110101 1101 . .... 0 ... .... .... .... @s_rrr_shi
}
RSB_rrri 1110101 1110 . .... 0 ... .... .... .... @s_rrr_shi
target/arm: Convert Data Processing (reg-shifted-reg) Convert the register shifted by register form of the data processing insns. For A32, we cannot yet remove any code because the legacy decoder intertwines the immediate form. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 22:29:54 +03:00
# Data-processing (register-shifted register)
MOV_rxrr 1111 1010 0 shty:2 s:1 rm:4 1111 rd:4 0000 rs:4 \
&s_rrr_shr rn=0
target/arm: Convert Data Processing (immediate) Convert the modified immediate form of the data processing insns. For A32, we can finally remove any code that was intertwined with the register and register-shifted-register forms. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190904193059.26202-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-04 22:29:55 +03:00
# Data-processing (immediate)
%t32extrot 26:1 12:3 0:8 !function=t32_expandimm_rot
%t32extimm 26:1 12:3 0:8 !function=t32_expandimm_imm
@s_rri_rot ....... .... s:1 rn:4 . ... rd:4 ........ \
&s_rri_rot imm=%t32extimm rot=%t32extrot
@s_rxi_rot ....... .... s:1 .... . ... rd:4 ........ \
&s_rri_rot imm=%t32extimm rot=%t32extrot rn=0
@S_xri_rot ....... .... . rn:4 . ... .... ........ \
&s_rri_rot imm=%t32extimm rot=%t32extrot s=1 rd=0
{
TST_xri 1111 0.0 0000 1 .... 0 ... 1111 ........ @S_xri_rot
AND_rri 1111 0.0 0000 . .... 0 ... .... ........ @s_rri_rot
}
BIC_rri 1111 0.0 0001 . .... 0 ... .... ........ @s_rri_rot
{
MOV_rxi 1111 0.0 0010 . 1111 0 ... .... ........ @s_rxi_rot
ORR_rri 1111 0.0 0010 . .... 0 ... .... ........ @s_rri_rot
}
{
MVN_rxi 1111 0.0 0011 . 1111 0 ... .... ........ @s_rxi_rot
ORN_rri 1111 0.0 0011 . .... 0 ... .... ........ @s_rri_rot
}
{
TEQ_xri 1111 0.0 0100 1 .... 0 ... 1111 ........ @S_xri_rot
EOR_rri 1111 0.0 0100 . .... 0 ... .... ........ @s_rri_rot
}
{
CMN_xri 1111 0.0 1000 1 .... 0 ... 1111 ........ @S_xri_rot
ADD_rri 1111 0.0 1000 . .... 0 ... .... ........ @s_rri_rot
}
ADC_rri 1111 0.0 1010 . .... 0 ... .... ........ @s_rri_rot
SBC_rri 1111 0.0 1011 . .... 0 ... .... ........ @s_rri_rot
{
CMP_xri 1111 0.0 1101 1 .... 0 ... 1111 ........ @S_xri_rot
SUB_rri 1111 0.0 1101 . .... 0 ... .... ........ @s_rri_rot
}
RSB_rri 1111 0.0 1110 . .... 0 ... .... ........ @s_rri_rot