hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
CXL uses PCI AER Internal errors to signal to the host that an error has
occurred. The host can then read more detailed status from the CXL RAS
capability.
For uncorrectable errors: support multiple injection in one operation
as this is needed to reliably test multiple header logging support in an
OS. The equivalent feature doesn't exist for correctable errors, so only
one error need be injected at a time.
Note:
- Header content needs to be manually specified in a fashion that
matches the specification for what can be in the header for each
error type.
Injection via QMP:
{ "execute": "qmp_capabilities" }
...
{ "execute": "cxl-inject-uncorrectable-errors",
"arguments": {
"path": "/machine/peripheral/cxl-pmem0",
"errors": [
{
"type": "cache-address-parity",
"header": [ 3, 4]
},
{
"type": "cache-data-parity",
"header": [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]
},
{
"type": "internal",
"header": [ 1, 2, 4]
}
]
}}
...
{ "execute": "cxl-inject-correctable-error",
"arguments": {
"path": "/machine/peripheral/cxl-pmem0",
"type": "physical"
} }
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20230302133709.30373-9-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02 16:37:09 +03:00
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qapi/qapi-commands-cxl.h"
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2023-05-30 16:36:01 +03:00
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void qmp_cxl_inject_general_media_event(const char *path, CxlEventLog log,
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uint8_t flags, uint64_t dpa,
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uint8_t descriptor, uint8_t type,
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uint8_t transaction_type,
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bool has_channel, uint8_t channel,
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bool has_rank, uint8_t rank,
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bool has_device, uint32_t device,
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const char *component_id,
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Error **errp) {}
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hw/cxl/events: Add injection of DRAM events
Defined in CXL r3.0 8.2.9.2.1.2 DRAM Event Record, this event
provides information related to DRAM devices.
Example injection command in QMP:
{ "execute": "cxl-inject-dram-event",
"arguments": {
"path": "/machine/peripheral/cxl-mem0",
"log": "informational",
"flags": 1,
"dpa": 1000,
"descriptor": 3,
"type": 3,
"transaction-type": 192,
"channel": 3,
"rank": 17,
"nibble-mask": 37421234,
"bank-group": 7,
"bank": 11,
"row": 2,
"column": 77,
"correction-mask": [33, 44, 55,66]
}}
Acked-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Fan Ni <fan.ni@samsung.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20230530133603.16934-7-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-05-30 16:36:02 +03:00
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void qmp_cxl_inject_dram_event(const char *path, CxlEventLog log, uint8_t flags,
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uint64_t dpa, uint8_t descriptor,
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uint8_t type, uint8_t transaction_type,
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bool has_channel, uint8_t channel,
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bool has_rank, uint8_t rank,
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bool has_nibble_mask, uint32_t nibble_mask,
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bool has_bank_group, uint8_t bank_group,
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bool has_bank, uint8_t bank,
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bool has_row, uint32_t row,
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bool has_column, uint16_t column,
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bool has_correction_mask, uint64List *correction_mask,
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Error **errp) {}
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2023-05-30 16:36:03 +03:00
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void qmp_cxl_inject_memory_module_event(const char *path, CxlEventLog log,
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uint8_t flags, uint8_t type,
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uint8_t health_status,
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uint8_t media_status,
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uint8_t additional_status,
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uint8_t life_used,
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int16_t temperature,
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uint32_t dirty_shutdown_count,
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uint32_t corrected_volatile_error_count,
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uint32_t corrected_persistent_error_count,
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Error **errp) {}
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2023-05-26 20:00:08 +03:00
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void qmp_cxl_inject_poison(const char *path, uint64_t start, uint64_t length,
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Error **errp)
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{
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error_setg(errp, "CXL Type 3 support is not compiled in");
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}
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hw/mem/cxl_type3: Add CXL RAS Error Injection Support.
CXL uses PCI AER Internal errors to signal to the host that an error has
occurred. The host can then read more detailed status from the CXL RAS
capability.
For uncorrectable errors: support multiple injection in one operation
as this is needed to reliably test multiple header logging support in an
OS. The equivalent feature doesn't exist for correctable errors, so only
one error need be injected at a time.
Note:
- Header content needs to be manually specified in a fashion that
matches the specification for what can be in the header for each
error type.
Injection via QMP:
{ "execute": "qmp_capabilities" }
...
{ "execute": "cxl-inject-uncorrectable-errors",
"arguments": {
"path": "/machine/peripheral/cxl-pmem0",
"errors": [
{
"type": "cache-address-parity",
"header": [ 3, 4]
},
{
"type": "cache-data-parity",
"header": [0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]
},
{
"type": "internal",
"header": [ 1, 2, 4]
}
]
}}
...
{ "execute": "cxl-inject-correctable-error",
"arguments": {
"path": "/machine/peripheral/cxl-pmem0",
"type": "physical"
} }
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20230302133709.30373-9-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-03-02 16:37:09 +03:00
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void qmp_cxl_inject_uncorrectable_errors(const char *path,
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CXLUncorErrorRecordList *errors,
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Error **errp)
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{
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error_setg(errp, "CXL Type 3 support is not compiled in");
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}
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void qmp_cxl_inject_correctable_error(const char *path, CxlCorErrorType type,
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Error **errp)
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{
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error_setg(errp, "CXL Type 3 support is not compiled in");
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}
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