mirror of https://github.com/proxmox/mirror_qemu
target-arm: Implement AArch64 view of CONTEXTIDR
Implement AArch64 view of the CONTEXTIDR register. We tighten up the condition when we flush the TLB on a CONTEXTIDR write to avoid needlessly flushing the TLB every time on a 64 bit system (and also on a 32 bit system using LPAE, as a bonus). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>master
parent
0ff644a786
commit
014406b510
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@ -201,7 +201,7 @@ typedef struct CPUARMState {
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uint64_t mair_el1;
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uint64_t mair_el1;
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uint64_t c12_vbar; /* vector base address register */
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uint64_t c12_vbar; /* vector base address register */
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uint32_t c13_fcse; /* FCSE PID. */
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uint32_t c13_fcse; /* FCSE PID. */
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uint32_t c13_context; /* Context ID. */
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uint64_t contextidr_el1; /* Context ID. */
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uint64_t tpidr_el0; /* User RW Thread register. */
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uint64_t tpidr_el0; /* User RW Thread register. */
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uint64_t tpidrro_el0; /* User RO Thread register. */
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uint64_t tpidrro_el0; /* User RO Thread register. */
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uint64_t tpidr_el1; /* Privileged Thread register. */
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uint64_t tpidr_el1; /* Privileged Thread register. */
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@ -304,6 +304,17 @@ void init_cpreg_list(ARMCPU *cpu)
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g_list_free(keys);
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g_list_free(keys);
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}
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}
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/* Return true if extended addresses are enabled.
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* This is always the case if our translation regime is 64 bit,
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* but depends on TTBCR.EAE for 32 bit.
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*/
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static inline bool extended_addresses_enabled(CPUARMState *env)
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{
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return arm_el_is_aa64(env, 1)
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|| ((arm_feature(env, ARM_FEATURE_LPAE)
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&& (env->cp15.c2_control & (1U << 31))));
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}
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static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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{
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{
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ARMCPU *cpu = arm_env_get_cpu(env);
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ARMCPU *cpu = arm_env_get_cpu(env);
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@ -330,14 +341,15 @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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{
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{
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ARMCPU *cpu = arm_env_get_cpu(env);
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ARMCPU *cpu = arm_env_get_cpu(env);
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if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
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if (env->cp15.contextidr_el1 != value && !arm_feature(env, ARM_FEATURE_MPU)
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&& !extended_addresses_enabled(env)) {
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/* For VMSA (when not using the LPAE long descriptor page table
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/* For VMSA (when not using the LPAE long descriptor page table
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* format) this register includes the ASID, so do a TLB flush.
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* format) this register includes the ASID, so do a TLB flush.
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* For PMSA it is purely a process ID and no action is needed.
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* For PMSA it is purely a process ID and no action is needed.
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*/
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*/
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tlb_flush(CPU(cpu), 1);
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tlb_flush(CPU(cpu), 1);
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}
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}
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env->cp15.c13_context = value;
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env->cp15.contextidr_el1 = value;
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}
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}
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static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
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@ -391,8 +403,10 @@ static const ARMCPRegInfo cp_reginfo[] = {
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{ .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
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{ .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
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.resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
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.resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
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{ .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
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{ .name = "CONTEXTIDR", .state = ARM_CP_STATE_BOTH,
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_context),
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.opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
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.access = PL1_RW,
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.fieldoffset = offsetof(CPUARMState, cp15.contextidr_el1),
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.resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
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.resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
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/* ??? This covers not just the impdef TLB lockdown registers but also
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/* ??? This covers not just the impdef TLB lockdown registers but also
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* some v7VMSA registers relating to TEX remap, so it is overly broad.
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* some v7VMSA registers relating to TEX remap, so it is overly broad.
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@ -1155,17 +1169,6 @@ static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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/* get_phys_addr() isn't present for user-mode-only targets */
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/* get_phys_addr() isn't present for user-mode-only targets */
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/* Return true if extended addresses are enabled.
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* This is always the case if our translation regime is 64 bit,
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* but depends on TTBCR.EAE for 32 bit.
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*/
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static inline bool extended_addresses_enabled(CPUARMState *env)
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{
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return arm_el_is_aa64(env, 1)
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|| ((arm_feature(env, ARM_FEATURE_LPAE)
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&& (env->cp15.c2_control & (1U << 31))));
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}
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static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
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static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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{
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if (ri->opc2 & 4) {
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if (ri->opc2 & 4) {
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