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target/m68k: move CCR/SR functions 

The following patches will be clearer if we move
functions before adding new ones.

Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20180104012913.30763-14-laurent@vivier.eu>
master
Laurent Vivier 2018-01-04 02:29:09 +01:00
parent fff3b4b0e1
commit 01490ea8f5
1 changed files with 55 additions and 56 deletions
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111
target/m68k/translate.c
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@ -2131,6 +2131,61 @@ DISAS_INSN(bitop_im)
}
}
static TCGv gen_get_ccr(DisasContext *s)
{
TCGv dest;
update_cc_op(s);
dest = tcg_temp_new();
gen_helper_get_ccr(dest, cpu_env);
return dest;
}
static TCGv gen_get_sr(DisasContext *s)
{
TCGv ccr;
TCGv sr;
ccr = gen_get_ccr(s);
sr = tcg_temp_new();
tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
tcg_gen_or_i32(sr, sr, ccr);
return sr;
}
static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
{
if (ccr_only) {
tcg_gen_movi_i32(QREG_CC_C, val & CCF_C ? 1 : 0);
tcg_gen_movi_i32(QREG_CC_V, val & CCF_V ? -1 : 0);
tcg_gen_movi_i32(QREG_CC_Z, val & CCF_Z ? 0 : 1);
tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0);
tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0);
} else {
gen_helper_set_sr(cpu_env, tcg_const_i32(val));
}
set_cc_op(s, CC_OP_FLAGS);
}
static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
int ccr_only)
{
if ((insn & 0x38) == 0) {
if (ccr_only) {
gen_helper_set_ccr(cpu_env, DREG(insn, 0));
} else {
gen_helper_set_sr(cpu_env, DREG(insn, 0));
}
set_cc_op(s, CC_OP_FLAGS);
} else if ((insn & 0x3f) == 0x3c) {
uint16_t val;
val = read_im16(env, s);
gen_set_sr_im(s, val, ccr_only);
} else {
disas_undef(env, s, insn);
}
}
DISAS_INSN(arith_im)
{
int op;
@ -2474,16 +2529,6 @@ DISAS_INSN(clr)
tcg_temp_free(zero);
}
static TCGv gen_get_ccr(DisasContext *s)
{
TCGv dest;
update_cc_op(s);
dest = tcg_temp_new();
gen_helper_get_ccr(dest, cpu_env);
return dest;
}
DISAS_INSN(move_from_ccr)
{
TCGv ccr;
@ -2510,40 +2555,6 @@ DISAS_INSN(neg)
tcg_temp_free(dest);
}
static void gen_set_sr_im(DisasContext *s, uint16_t val, int ccr_only)
{
if (ccr_only) {
tcg_gen_movi_i32(QREG_CC_C, val & CCF_C ? 1 : 0);
tcg_gen_movi_i32(QREG_CC_V, val & CCF_V ? -1 : 0);
tcg_gen_movi_i32(QREG_CC_Z, val & CCF_Z ? 0 : 1);
tcg_gen_movi_i32(QREG_CC_N, val & CCF_N ? -1 : 0);
tcg_gen_movi_i32(QREG_CC_X, val & CCF_X ? 1 : 0);
} else {
gen_helper_set_sr(cpu_env, tcg_const_i32(val));
}
set_cc_op(s, CC_OP_FLAGS);
}
static void gen_set_sr(CPUM68KState *env, DisasContext *s, uint16_t insn,
int ccr_only)
{
if ((insn & 0x38) == 0) {
if (ccr_only) {
gen_helper_set_ccr(cpu_env, DREG(insn, 0));
} else {
gen_helper_set_sr(cpu_env, DREG(insn, 0));
}
set_cc_op(s, CC_OP_FLAGS);
} else if ((insn & 0x3f) == 0x3c) {
uint16_t val;
val = read_im16(env, s);
gen_set_sr_im(s, val, ccr_only);
} else {
disas_undef(env, s, insn);
}
}
DISAS_INSN(move_to_ccr)
{
gen_set_sr(env, s, insn, 1);
@ -4359,18 +4370,6 @@ DISAS_INSN(move16_mem)
}
}
static TCGv gen_get_sr(DisasContext *s)
{
TCGv ccr;
TCGv sr;
ccr = gen_get_ccr(s);
sr = tcg_temp_new();
tcg_gen_andi_i32(sr, QREG_SR, 0xffe0);
tcg_gen_or_i32(sr, sr, ccr);
return sr;
}
DISAS_INSN(strldsr)
{
uint16_t ext;