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Fixes and more queued patches 

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Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20170113' into staging

Fixes and more queued patches

# gpg: Signature made Fri 13 Jan 2017 20:00:53 GMT
# gpg:                using RSA key 0xAD1270CC4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg:                 aka "Richard Henderson <rth@redhat.com>"
# gpg:                 aka "Richard Henderson <rth@twiddle.net>"
# Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC  16A4 AD12 70CC 4DD0 279B

* remotes/rth/tags/pull-tcg-20170113:
  tcg/aarch64: Fix tcg_out_movi
  tcg/aarch64: Fix addsub2 for 0+C
  target/arm: Fix ubfx et al for aarch64
  tcg/s390: Fix merge error with facilities

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
master
Peter Maydell 2017-01-16 11:17:38 +00:00
parent b6af8ea602 8cf9a3d3f7
commit 02f50ca0de
3 changed files with 35 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
target/arm/translate-a64.c
View File

@ -3217,7 +3217,7 @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
tcg_tmp = read_cpu_reg(s, rn, 1);
/* Recognize simple(r) extractions. */
if (si <= ri) {
if (si >= ri) {
/* Wd<s-r:0> = Wn<s:r> */
len = (si - ri) + 1;
if (opc == 0) { /* SBFM: ASR, SBFX, SXTB, SXTH, SXTW */

66
tcg/aarch64/tcg-target.inc.c
View File

@ -580,11 +580,9 @@ static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext,
static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
tcg_target_long value)
{
AArch64Insn insn;
int i, wantinv, shift;
tcg_target_long svalue = value;
tcg_target_long ivalue = ~value;
tcg_target_long imask;
/* For 32-bit values, discard potential garbage in value. For 64-bit
values within [2**31, 2**32-1], we can create smaller sequences by
@ -630,42 +628,35 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
/* Would it take fewer insns to begin with MOVN? For the value and its
inverse, count the number of 16-bit lanes that are 0. */
for (i = wantinv = imask = 0; i < 64; i += 16) {
for (i = wantinv = 0; i < 64; i += 16) {
tcg_target_long mask = 0xffffull << i;
if ((value & mask) == 0) {
wantinv -= 1;
}
if ((ivalue & mask) == 0) {
wantinv += 1;
imask |= mask;
}
wantinv -= ((value & mask) == 0);
wantinv += ((ivalue & mask) == 0);
}
/* If we had more 0xffff than 0x0000, invert VALUE and use MOVN. */
insn = I3405_MOVZ;
if (wantinv > 0) {
value = ivalue;
insn = I3405_MOVN;
}
/* Find the lowest lane that is not 0x0000. */
shift = ctz64(value) & (63 & -16);
tcg_out_insn_3405(s, insn, type, rd, value >> shift, shift);
if (wantinv > 0) {
/* Re-invert the value, so MOVK sees non-inverted bits. */
value = ~value;
/* Clear out all the 0xffff lanes. */
value ^= imask;
}
/* Clear out the lane that we just set. */
value &= ~(0xffffUL << shift);
/* Iterate until all lanes have been set, and thus cleared from VALUE. */
while (value) {
if (wantinv <= 0) {
/* Find the lowest lane that is not 0x0000. */
shift = ctz64(value) & (63 & -16);
tcg_out_insn(s, 3405, MOVK, type, rd, value >> shift, shift);
tcg_out_insn(s, 3405, MOVZ, type, rd, value >> shift, shift);
/* Clear out the lane that we just set. */
value &= ~(0xffffUL << shift);
/* Iterate until all non-zero lanes have been processed. */
while (value) {
shift = ctz64(value) & (63 & -16);
tcg_out_insn(s, 3405, MOVK, type, rd, value >> shift, shift);
value &= ~(0xffffUL << shift);
}
} else {
/* Like above, but with the inverted value and MOVN to start. */
shift = ctz64(ivalue) & (63 & -16);
tcg_out_insn(s, 3405, MOVN, type, rd, ivalue >> shift, shift);
ivalue &= ~(0xffffUL << shift);
while (ivalue) {
shift = ctz64(ivalue) & (63 & -16);
/* Provide MOVK with the non-inverted value. */
tcg_out_insn(s, 3405, MOVK, type, rd, ~(ivalue >> shift), shift);
ivalue &= ~(0xffffUL << shift);
}
}
}
@ -964,6 +955,15 @@ static inline void tcg_out_addsub2(TCGContext *s, int ext, TCGReg rl,
insn = I3401_SUBSI;
bl = -bl;
}
if (unlikely(al == TCG_REG_XZR)) {
/* ??? We want to allow al to be zero for the benefit of
negation via subtraction. However, that leaves open the
possibility of adding 0+const in the low part, and the
immediate add instructions encode XSP not XZR. Don't try
anything more elaborate here than loading another zero. */
al = TCG_REG_TMP;
tcg_out_movi(s, ext, al, 0);
}
tcg_out_insn_3401(s, insn, ext, rl, al, bl);
} else {
tcg_out_insn_3502(s, sub ? I3502_SUBS : I3502_ADDS, ext, rl, al, bl);

2
tcg/s390/tcg-target.inc.c
View File

@ -1096,7 +1096,7 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1,
/* If we only got here because of load-and-test,
and we couldn't use that, then we need to load
the constant into a register. */
if (!(facilities & FACILITY_EXT_IMM)) {
if (!(s390_facilities & FACILITY_EXT_IMM)) {
c2 = TCG_TMP0;
tcg_out_movi(s, type, c2, 0);
goto do_reg;