mirror of https://github.com/proxmox/mirror_qemu
target-ppc: emulate load doubleword pair instructions
Needed for Power ISA version 2.05 compliance. The check for odd register pairs is done using the invalid bits. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>master
parent
199f830d19
commit
05050ee804
|
@ -3300,6 +3300,52 @@ GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
|
||||||
/* lfs lfsu lfsux lfsx */
|
/* lfs lfsu lfsux lfsx */
|
||||||
GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
|
GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
|
||||||
|
|
||||||
|
/* lfdp */
|
||||||
|
static void gen_lfdp(DisasContext *ctx)
|
||||||
|
{
|
||||||
|
TCGv EA;
|
||||||
|
if (unlikely(!ctx->fpu_enabled)) {
|
||||||
|
gen_exception(ctx, POWERPC_EXCP_FPU);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
gen_set_access_type(ctx, ACCESS_FLOAT);
|
||||||
|
EA = tcg_temp_new();
|
||||||
|
gen_addr_imm_index(ctx, EA, 0); \
|
||||||
|
if (unlikely(ctx->le_mode)) {
|
||||||
|
gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
|
||||||
|
tcg_gen_addi_tl(EA, EA, 8);
|
||||||
|
gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
|
||||||
|
} else {
|
||||||
|
gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
|
||||||
|
tcg_gen_addi_tl(EA, EA, 8);
|
||||||
|
gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
|
||||||
|
}
|
||||||
|
tcg_temp_free(EA);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* lfdpx */
|
||||||
|
static void gen_lfdpx(DisasContext *ctx)
|
||||||
|
{
|
||||||
|
TCGv EA;
|
||||||
|
if (unlikely(!ctx->fpu_enabled)) {
|
||||||
|
gen_exception(ctx, POWERPC_EXCP_FPU);
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
gen_set_access_type(ctx, ACCESS_FLOAT);
|
||||||
|
EA = tcg_temp_new();
|
||||||
|
gen_addr_reg_index(ctx, EA);
|
||||||
|
if (unlikely(ctx->le_mode)) {
|
||||||
|
gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
|
||||||
|
tcg_gen_addi_tl(EA, EA, 8);
|
||||||
|
gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
|
||||||
|
} else {
|
||||||
|
gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
|
||||||
|
tcg_gen_addi_tl(EA, EA, 8);
|
||||||
|
gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
|
||||||
|
}
|
||||||
|
tcg_temp_free(EA);
|
||||||
|
}
|
||||||
|
|
||||||
/* lfiwax */
|
/* lfiwax */
|
||||||
static void gen_lfiwax(DisasContext *ctx)
|
static void gen_lfiwax(DisasContext *ctx)
|
||||||
{
|
{
|
||||||
|
@ -9035,6 +9081,8 @@ GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
|
||||||
GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
|
GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
|
||||||
GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
|
GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
|
||||||
GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
|
GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
|
||||||
|
GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
|
||||||
|
GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
|
||||||
|
|
||||||
#undef GEN_STF
|
#undef GEN_STF
|
||||||
#undef GEN_STUF
|
#undef GEN_STUF
|
||||||
|
|
Loading…
Reference in New Issue