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target-mips: Streamline indexed cp1 memory addressing. 

We've already eliminated both base and index being zero.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
master
Richard Henderson 2012-03-30 13:16:36 -04:00 committed by Aurelien Jarno
parent 13d24f4972
commit 0516867450
1 changed files with 1 additions and 2 deletions
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3
target-mips/translate.c
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@ -7742,8 +7742,7 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc,
} else if (index == 0) { } else if (index == 0) {
gen_load_gpr(t0, base); gen_load_gpr(t0, base);
} else { } else {
gen_load_gpr(t0, index); gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[index]);
gen_op_addr_add(ctx, t0, cpu_gpr[base], t0);
} }
/* Don't do NOP if destination is zero: we must perform the actual /* Don't do NOP if destination is zero: we must perform the actual
memory access. */ memory access. */