mirror of https://github.com/proxmox/mirror_qemu
target/mips: Clean up translate.c
Mostly fix errors and warnings reported by 'checkpatch.pl -f'. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <1569331602-2586-7-git-send-email-aleksandar.markovic@rt-rk.com>master
parent
f823213c22
commit
05aa7e934b
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@ -7118,7 +7118,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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tcg_gen_andi_tl(arg, arg, ~0xffff);
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register_name = "BadInstrX";
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break;
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default:
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default:
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goto cp0_unimplemented;
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}
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break;
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@ -7545,7 +7545,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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case CP0_REG31__KSCRATCH6:
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CP0_CHECK(ctx->kscrexist & (1 << sel));
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tcg_gen_ld_tl(arg, cpu_env,
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offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
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offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
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tcg_gen_ext32s_tl(arg, arg);
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register_name = "KScratch";
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break;
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@ -8295,7 +8295,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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case CP0_REG31__KSCRATCH6:
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CP0_CHECK(ctx->kscrexist & (1 << sel));
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tcg_gen_st_tl(arg, cpu_env,
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offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
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offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
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register_name = "KScratch";
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break;
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default:
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@ -8387,17 +8387,20 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REG01__YQMASK:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMask));
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tcg_gen_ld_tl(arg, cpu_env,
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offsetof(CPUMIPSState, CP0_YQMask));
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register_name = "YQMask";
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break;
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case CP0_REG01__VPESCHEDULE:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
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tcg_gen_ld_tl(arg, cpu_env,
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offsetof(CPUMIPSState, CP0_VPESchedule));
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register_name = "VPESchedule";
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break;
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case CP0_REG01__VPESCHEFBACK:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
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tcg_gen_ld_tl(arg, cpu_env,
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offsetof(CPUMIPSState, CP0_VPEScheFBack));
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register_name = "VPEScheFBack";
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break;
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case CP0_REG01__VPEOPT:
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@ -8412,7 +8415,8 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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case CP0_REGISTER_02:
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switch (sel) {
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case CP0_REG02__ENTRYLO0:
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tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
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tcg_gen_ld_tl(arg, cpu_env,
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offsetof(CPUMIPSState, CP0_EntryLo0));
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register_name = "EntryLo0";
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break;
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case CP0_REG02__TCSTATUS:
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@ -8756,7 +8760,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
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register_name = "Config5";
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break;
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/* 6,7 are implementation dependent */
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/* 6,7 are implementation dependent */
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case CP0_REG16__CONFIG6:
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
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register_name = "Config6";
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@ -8837,7 +8841,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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}
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break;
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case CP0_REGISTER_21:
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/* Officially reserved, but sel 0 is used for R1x000 framemask */
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/* Officially reserved, but sel 0 is used for R1x000 framemask */
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CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
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switch (sel) {
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case 0:
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@ -9022,7 +9026,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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case CP0_REG31__KSCRATCH6:
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CP0_CHECK(ctx->kscrexist & (1 << sel));
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tcg_gen_ld_tl(arg, cpu_env,
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offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
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offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
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register_name = "KScratch";
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break;
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default:
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@ -9112,12 +9116,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REG01__VPESCHEDULE:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
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tcg_gen_st_tl(arg, cpu_env,
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offsetof(CPUMIPSState, CP0_VPESchedule));
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register_name = "VPESchedule";
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break;
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case CP0_REG01__VPESCHEFBACK:
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CP0_CHECK(ctx->insn_flags & ASE_MT);
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tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
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tcg_gen_st_tl(arg, cpu_env,
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offsetof(CPUMIPSState, CP0_VPEScheFBack));
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register_name = "VPEScheFBack";
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break;
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case CP0_REG01__VPEOPT:
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