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MIPS hardware updates 

- MAINTAINERS updated to welcome Huacai Chen and Jiaxun Yang,
   and update Aleksandar Rikalo's email address,
 - Trivial improvements in the Bonito64 North Bridge and the
   Fuloong 2e machine,
 - MIPS Machines names unified without 'mips_' prefix.
 
 CI: https://travis-ci.org/github/philmd/qemu/builds/691247975
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Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-hw-next-20200526' into staging

MIPS hardware updates

- MAINTAINERS updated to welcome Huacai Chen and Jiaxun Yang,
  and update Aleksandar Rikalo's email address,
- Trivial improvements in the Bonito64 North Bridge and the
  Fuloong 2e machine,
- MIPS Machines names unified without 'mips_' prefix.

CI: https://travis-ci.org/github/philmd/qemu/builds/691247975

# gpg: Signature made Tue 26 May 2020 14:32:08 BST
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd-gitlab/tags/mips-hw-next-20200526:
  MAINTAINERS: Change Aleksandar Rikalo's email address
  hw/mips/mips_int: De-duplicate KVM interrupt delivery
  hw/mips/malta: Add some logging for bad register offset cases
  hw/mips: Rename malta/mipssim/r4k/jazz files
  hw/mips/fuloong2e: Fix typo in Fuloong machine name
  hw/mips/fuloong2e: Move code and update a comment
  hw/pci-host/bonito: Set the Config register reset value with FIELD_DP32
  hw/pci-host/bonito: Better describe the I/O CS regions
  hw/pci-host/bonito: Map the different PCI ranges more detailed
  hw/pci-host/bonito: Map all the Bonito64 I/O range
  hw/pci-host/bonito: Map peripheral using physical address
  hw/pci-host/bonito: Fix DPRINTF() format strings
  hw/pci-host: Use CONFIG_PCI_BONITO to select the Bonito North Bridge
  MAINTAINERS: Add Huacai Chen as fuloong2e co-maintainer

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
master
Peter Maydell 2020-05-26 20:25:06 +01:00
parent ddc760832f 97d8974620
commit 06539ebc76
18 changed files with 142 additions and 80 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
.mailmap
View File

@ -42,7 +42,8 @@ Justin Terry (VM) <juterry@microsoft.com> Justin Terry (VM) via Qemu-devel <qemu
Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> <aleksandar.markovic@mips.com>
Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> <aleksandar.markovic@imgtec.com>
Aleksandar Markovic <aleksandar.qemu.devel@gmail.com> <amarkovic@wavecomp.com>
Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> <arikalo@wavecomp.com>
Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> <arikalo@wavecomp.com>
Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> <aleksandar.rikalo@rt-rk.com>
Anthony Liguori <anthony@codemonkey.ws> Anthony Liguori <aliguori@us.ibm.com>
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
Leif Lindholm <leif@nuviainc.com> <leif.lindholm@linaro.org>

26
MAINTAINERS
View File

@ -213,7 +213,7 @@ F: disas/microblaze.c
MIPS TCG CPUs
M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
R: Aurelien Jarno <aurelien@aurel32.net>
R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
S: Maintained
F: target/mips/
F: default-configs/*mips*
@ -1048,9 +1048,9 @@ MIPS Machines
-------------
Jazz
M: Hervé Poussineau <hpoussin@reactos.org>
R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
S: Maintained
F: hw/mips/mips_jazz.c
F: hw/mips/jazz.c
F: hw/display/jazz_led.c
F: hw/dma/rc4030.c
@ -1061,7 +1061,7 @@ R: Aurelien Jarno <aurelien@aurel32.net>
S: Maintained
F: hw/isa/piix4.c
F: hw/acpi/piix4.c
F: hw/mips/mips_malta.c
F: hw/mips/malta.c
F: hw/mips/gt64xxx_pci.c
F: include/hw/southbridge/piix.h
F: tests/acceptance/linux_ssh_mips_malta.py
@ -1069,30 +1069,32 @@ F: tests/acceptance/machine_mips_malta.py
Mipssim
M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
S: Odd Fixes
F: hw/mips/mips_mipssim.c
F: hw/mips/mipssim.c
F: hw/net/mipsnet.c
R4000
M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
R: Aurelien Jarno <aurelien@aurel32.net>
R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
S: Obsolete
F: hw/mips/mips_r4k.c
F: hw/mips/r4k.c
Fulong 2E
Fuloong 2E
M: Huacai Chen <chenhc@lemote.com>
M: Philippe Mathieu-Daudé <f4bug@amsat.org>
M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
R: Jiaxun Yang <jiaxun.yang@flygoat.com>
S: Odd Fixes
F: hw/mips/mips_fulong2e.c
F: hw/mips/fuloong2e.c
F: hw/isa/vt82c686.c
F: hw/pci-host/bonito.c
F: include/hw/isa/vt82c686.h
Boston
M: Paul Burton <pburton@wavecomp.com>
R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
S: Maintained
F: hw/core/loader-fit.c
F: hw/mips/boston.c
@ -2606,7 +2608,7 @@ F: disas/i386.c
MIPS TCG target
M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
R: Aurelien Jarno <aurelien@aurel32.net>
R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>
S: Maintained
F: tcg/mips/

2
default-configs/mips64el-softmmu.mak
View File

@ -2,7 +2,7 @@
include mips-softmmu-common.mak
CONFIG_IDE_VIA=y
CONFIG_FULONG=y
CONFIG_FULOONG=y
CONFIG_ATI_VGA=y
CONFIG_RTL8139_PCI=y
CONFIG_JAZZ=y

5
docs/system/deprecated.rst
View File

@ -368,6 +368,11 @@ mips ``r4k`` platform (since 5.0)
This machine type is very old and unmaintained. Users should use the ``malta``
machine type instead.
mips ``fulong2e`` machine (since 5.1)
'''''''''''''''''''''''''''''''''''''
This machine has been renamed ``fuloong2e``.
``pc-1.0``, ``pc-1.1``, ``pc-1.2`` and ``pc-1.3`` (since 5.0)
'''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''

2
docs/system/target-mips.rst
View File

@ -74,7 +74,7 @@ The MIPS Magnum R4000 emulation supports:
- G364 framebuffer
The Fulong 2E emulation supports:
The Fuloong 2E emulation supports:
- Loongson 2E CPU

2
hw/isa/vt82c686.c
View File

@ -503,7 +503,7 @@ static void via_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_via;
/*
* Reason: part of VIA VT82C686 southbridge, needs to be wired up,
* e.g. by mips_fulong2e_init()
* e.g. by mips_fuloong2e_init()
*/
dc->user_creatable = false;
}

3
hw/mips/Kconfig
View File

@ -41,8 +41,9 @@ config JAZZ
select DS1225Y
select JAZZ_LED
config FULONG
config FULOONG
bool
select PCI_BONITO
config MIPS_CPS
bool

10
hw/mips/Makefile.objs
View File

@ -1,8 +1,8 @@
obj-y += addr.o mips_int.o
obj-$(CONFIG_R4K) += mips_r4k.o
obj-$(CONFIG_MALTA) += gt64xxx_pci.o mips_malta.o
obj-$(CONFIG_MIPSSIM) += mips_mipssim.o
obj-$(CONFIG_JAZZ) += mips_jazz.o
obj-$(CONFIG_FULONG) += mips_fulong2e.o
obj-$(CONFIG_R4K) += r4k.o
obj-$(CONFIG_MALTA) += gt64xxx_pci.o malta.o
obj-$(CONFIG_MIPSSIM) += mipssim.o
obj-$(CONFIG_JAZZ) += jazz.o
obj-$(CONFIG_FULOONG) += fuloong2e.o
obj-$(CONFIG_MIPS_CPS) += cps.o
obj-$(CONFIG_MIPS_BOSTON) += boston.o

48
hw/mips/mips_fulong2e.c → hw/mips/fuloong2e.c
View File

@ -1,5 +1,5 @@
/*
* QEMU fulong 2e mini pc support
* QEMU fuloong 2e mini pc support
*
* Copyright (c) 2008 yajin (yajin@vm-kernel.org)
* Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
@ -11,8 +11,8 @@
*/
/*
* Fulong 2e mini pc is based on ICT/ST Loongson 2e CPU (MIPS III like, 800MHz)
* http://www.linux-mips.org/wiki/Fulong
* Fuloong 2e mini pc is based on ICT/ST Loongson 2e CPU (MIPS III like, 800MHz)
* https://www.linux-mips.org/wiki/Fuloong_2E
*
* Loongson 2e user manual:
* http://www.loongsondeveloper.com/doc/Loongson2EUserGuide.pdf
@ -45,13 +45,13 @@
#include "sysemu/reset.h"
#include "qemu/error-report.h"
#define DEBUG_FULONG2E_INIT
#define DEBUG_FULOONG2E_INIT
#define ENVP_ADDR 0x80002000l
#define ENVP_NB_ENTRIES 16
#define ENVP_ENTRY_SIZE 256
/* fulong 2e has a 512k flash: Winbond W39L040AP70Z */
/* Fuloong 2e has a 512k flash: Winbond W39L040AP70Z */
#define BIOS_SIZE (512 * KiB)
#define MAX_IDE_BUS 2
@ -68,12 +68,12 @@
* 2, use "Bonito2edev" to replace "dir_corresponding_to_your_target_hardware"
* in the "Compile Guide".
*/
#define FULONG_BIOSNAME "pmon_fulong2e.bin"
#define FULOONG_BIOSNAME "pmon_2e.bin"
/* PCI SLOT in fulong 2e */
#define FULONG2E_VIA_SLOT 5
#define FULONG2E_ATI_SLOT 6
#define FULONG2E_RTL8139_SLOT 7
/* PCI SLOT in Fuloong 2e */
#define FULOONG2E_VIA_SLOT 5
#define FULOONG2E_ATI_SLOT 6
#define FULOONG2E_RTL8139_SLOT 7
static struct _loaderparams {
int ram_size;
@ -278,7 +278,7 @@ static void network_init(PCIBus *pci_bus)
const char *default_devaddr = NULL;
if (i == 0 && (!nd->model || strcmp(nd->model, "rtl8139") == 0)) {
/* The fulong board has a RTL8139 card using PCI SLOT 7 */
/* The Fuloong board has a RTL8139 card using PCI SLOT 7 */
default_devaddr = "07";
}
@ -286,7 +286,7 @@ static void network_init(PCIBus *pci_bus)
}
}
static void mips_fulong2e_init(MachineState *machine)
static void mips_fuloong2e_init(MachineState *machine)
{
const char *kernel_filename = machine->kernel_filename;
const char *kernel_cmdline = machine->kernel_cmdline;
@ -315,12 +315,11 @@ static void mips_fulong2e_init(MachineState *machine)
error_report("Invalid RAM size, should be 256MB");
exit(EXIT_FAILURE);
}
/* allocate RAM */
memory_region_init_rom(bios, NULL, "fulong2e.bios", BIOS_SIZE,
&error_fatal);
memory_region_add_subregion(address_space_mem, 0, machine->ram);
/* Boot ROM */
memory_region_init_rom(bios, NULL, "fuloong2e.bios", BIOS_SIZE,
&error_fatal);
memory_region_add_subregion(address_space_mem, 0x1fc00000LL, bios);
/*
@ -337,7 +336,7 @@ static void mips_fulong2e_init(MachineState *machine)
write_bootloader(env, memory_region_get_ram_ptr(bios), kernel_entry);
} else {
if (bios_name == NULL) {
bios_name = FULONG_BIOSNAME;
bios_name = FULOONG_BIOSNAME;
}
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
if (filename) {
@ -363,7 +362,7 @@ static void mips_fulong2e_init(MachineState *machine)
pci_bus = bonito_init((qemu_irq *)&(env->irq[2]));
/* South bridge -> IP5 */
vt82c686b_southbridge_init(pci_bus, FULONG2E_VIA_SLOT, env->irq[5],
vt82c686b_southbridge_init(pci_bus, FULOONG2E_VIA_SLOT, env->irq[5],
&smbus, &isa_bus);
/* GPU */
@ -384,14 +383,15 @@ static void mips_fulong2e_init(MachineState *machine)
network_init(pci_bus);
}
static void mips_fulong2e_machine_init(MachineClass *mc)
static void mips_fuloong2e_machine_init(MachineClass *mc)
{
mc->desc = "Fulong 2e mini pc";
mc->init = mips_fulong2e_init;
mc->desc = "Fuloong 2e mini pc";
mc->alias = "fulong2e"; /* Incorrect name used up to QEMU 4.2 */
mc->init = mips_fuloong2e_init;
mc->block_default_type = IF_IDE;
mc->default_cpu_type = MIPS_CPU_TYPE_NAME("Loongson-2E");
mc->default_ram_size = 256 * MiB;
mc->default_ram_id = "fulong2e.ram";
mc->default_ram_id = "fuloong2e.ram";
}
DEFINE_MACHINE("fulong2e", mips_fulong2e_machine_init)
DEFINE_MACHINE("fuloong2e", mips_fuloong2e_machine_init)

0
hw/mips/mips_jazz.c → hw/mips/jazz.c
View File

14
hw/mips/mips_malta.c → hw/mips/malta.c
View File

@ -427,10 +427,9 @@ static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
break;
default:
#if 0
printf("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
addr);
#endif
qemu_log_mask(LOG_GUEST_ERROR,
"malta_fpga_read: Bad register addr 0x%"HWADDR_PRIX"\n",
addr);
break;
}
return val;
@ -515,10 +514,9 @@ static void malta_fpga_write(void *opaque, hwaddr addr,
break;
default:
#if 0
printf("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
addr);
#endif
qemu_log_mask(LOG_GUEST_ERROR,
"malta_fpga_write: Bad register addr 0x%"HWADDR_PRIX"\n",
addr);
break;
}
}

11
hw/mips/mips_int.c
View File

@ -47,17 +47,12 @@ static void cpu_mips_irq_request(void *opaque, int irq, int level)
if (level) {
env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
if (kvm_enabled() && irq == 2) {
kvm_mips_set_interrupt(cpu, irq, level);
}
} else {
env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP));
}
if (kvm_enabled() && irq == 2) {
kvm_mips_set_interrupt(cpu, irq, level);
}
if (kvm_enabled() && irq == 2) {
kvm_mips_set_interrupt(cpu, irq, level);
}
if (env->CP0_Cause & CP0Ca_IP_mask) {

0
hw/mips/mips_mipssim.c → hw/mips/mipssim.c
View File

0
hw/mips/mips_r4k.c → hw/mips/r4k.c
View File

5
hw/pci-host/Kconfig
View File

@ -55,3 +55,8 @@ config PCI_EXPRESS_DESIGNWARE
bool
select PCI_EXPRESS
select MSI_NONBROKEN
config PCI_BONITO
select PCI
select UNIMP
bool

2
hw/pci-host/Makefile.objs
View File

@ -12,7 +12,7 @@ common-obj-$(CONFIG_PPCE500_PCI) += ppce500.o
common-obj-$(CONFIG_VERSATILE_PCI) += versatile.o
common-obj-$(CONFIG_PCI_SABRE) += sabre.o
common-obj-$(CONFIG_FULONG) += bonito.o
common-obj-$(CONFIG_PCI_BONITO) += bonito.o
common-obj-$(CONFIG_PCI_I440FX) += i440fx.o
common-obj-$(CONFIG_XEN_IGD_PASSTHROUGH) += xen_igd_pt.o
common-obj-$(CONFIG_PCI_EXPRESS_Q35) += q35.o

87
hw/pci-host/bonito.c
View File

@ -11,7 +11,7 @@
*/
/*
* fulong 2e mini pc has a bonito north bridge.
* fuloong 2e mini pc has a bonito north bridge.
*/
/*
@ -39,6 +39,7 @@
*/
#include "qemu/osdep.h"
#include "qemu/units.h"
#include "qemu/error-report.h"
#include "hw/pci/pci.h"
#include "hw/irq.h"
@ -48,6 +49,8 @@
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
#include "exec/address-spaces.h"
#include "hw/misc/unimp.h"
#include "hw/registerfields.h"
/* #define DEBUG_BONITO */
@ -81,7 +84,7 @@
#define BONITO_PCILO1_BASE 0x14000000
#define BONITO_PCILO2_BASE 0x18000000
#define BONITO_PCIHI_BASE 0x20000000
#define BONITO_PCIHI_SIZE 0x20000000
#define BONITO_PCIHI_SIZE 0x60000000
#define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE - 1)
#define BONITO_PCIIO_BASE 0x1fd00000
#define BONITO_PCIIO_BASE_VA 0xbfd00000
@ -110,8 +113,19 @@
/* Power on register */
#define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */
/* PCI configuration register */
#define BONITO_BONGENCFG_OFFSET 0x4
#define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET >> 2) /*0x104 */
REG32(BONGENCFG, 0x104)
FIELD(BONGENCFG, DEBUGMODE, 0, 1)
FIELD(BONGENCFG, SNOOP, 1, 1)
FIELD(BONGENCFG, CPUSELFRESET, 2, 1)
FIELD(BONGENCFG, BYTESWAP, 6, 1)
FIELD(BONGENCFG, UNCACHED, 7, 1)
FIELD(BONGENCFG, PREFETCH, 8, 1)
FIELD(BONGENCFG, WRITEBEHIND, 9, 1)
FIELD(BONGENCFG, PCIQUEUE, 12, 1)
/* 2. IO & IDE configuration */
#define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */
@ -239,7 +253,7 @@ static void bonito_writel(void *opaque, hwaddr addr,
saddr = addr >> 2;
DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x\n",
DPRINTF("bonito_writel "TARGET_FMT_plx" val %lx saddr %x\n",
addr, val, saddr);
switch (saddr) {
case BONITO_BONPONCFG:
@ -327,7 +341,7 @@ static void bonito_pciconf_writel(void *opaque, hwaddr addr,
PCIBonitoState *s = opaque;
PCIDevice *d = PCI_DEVICE(s);
DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x\n", addr, val);
DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %lx\n", addr, val);
d->config_write(d, addr, val, 4);
}
@ -474,7 +488,7 @@ static void bonito_spciconf_write(void *opaque, hwaddr addr, uint64_t val,
uint32_t pciaddr;
uint16_t status;
DPRINTF("bonito_spciconf_write "TARGET_FMT_plx" size %d val %x\n",
DPRINTF("bonito_spciconf_write "TARGET_FMT_plx" size %d val %lx\n",
addr, size, val);
pciaddr = bonito_sbridge_pciaddr(s, addr);
@ -559,11 +573,11 @@ static int pci_bonito_map_irq(PCIDevice *pci_dev, int irq_num)
slot = (pci_dev->devfn >> 3);
switch (slot) {
case 5: /* FULONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */
case 5: /* FULOONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */
return irq_num % 4 + BONITO_IRQ_BASE;
case 6: /* FULONG2E_ATI_SLOT, VGA */
case 6: /* FULOONG2E_ATI_SLOT, VGA */
return 4 + BONITO_IRQ_BASE;
case 7: /* FULONG2E_RTL_SLOT, RTL8139 */
case 7: /* FULOONG2E_RTL_SLOT, RTL8139 */
return 5 + BONITO_IRQ_BASE;
case 8 ... 12: /* PCI slot 1 to 4 */
return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE;
@ -575,11 +589,18 @@ static int pci_bonito_map_irq(PCIDevice *pci_dev, int irq_num)
static void bonito_reset(void *opaque)
{
PCIBonitoState *s = opaque;
uint32_t val = 0;
/* set the default value of north bridge registers */
s->regs[BONITO_BONPONCFG] = 0xc40;
s->regs[BONITO_BONGENCFG] = 0x1384;
val = FIELD_DP32(val, BONGENCFG, PCIQUEUE, 1);
val = FIELD_DP32(val, BONGENCFG, WRITEBEHIND, 1);
val = FIELD_DP32(val, BONGENCFG, PREFETCH, 1);
val = FIELD_DP32(val, BONGENCFG, UNCACHED, 1);
val = FIELD_DP32(val, BONGENCFG, CPUSELFRESET, 1);
s->regs[BONITO_BONGENCFG] = val;
s->regs[BONITO_IODEVCFG] = 0x2bff8010;
s->regs[BONITO_SDCFG] = 0x255e0091;
@ -604,14 +625,26 @@ static void bonito_pcihost_realize(DeviceState *dev, Error **errp)
{
PCIHostState *phb = PCI_HOST_BRIDGE(dev);
BonitoState *bs = BONITO_PCI_HOST_BRIDGE(dev);
MemoryRegion *pcimem_lo_alias = g_new(MemoryRegion, 3);
memory_region_init(&bs->pci_mem, OBJECT(dev), "pci.mem", BONITO_PCILO_SIZE);
memory_region_init(&bs->pci_mem, OBJECT(dev), "pci.mem", BONITO_PCIHI_SIZE);
phb->bus = pci_register_root_bus(dev, "pci",
pci_bonito_set_irq, pci_bonito_map_irq,
dev, &bs->pci_mem, get_system_io(),
0x28, 32, TYPE_PCI_BUS);
memory_region_add_subregion(get_system_memory(), BONITO_PCILO_BASE,
&bs->pci_mem);
for (size_t i = 0; i < 3; i++) {
char *name = g_strdup_printf("pci.lomem%zu", i);
memory_region_init_alias(&pcimem_lo_alias[i], NULL, name,
&bs->pci_mem, i * 64 * MiB, 64 * MiB);
memory_region_add_subregion(get_system_memory(),
BONITO_PCILO_BASE + i * 64 * MiB,
&pcimem_lo_alias[i]);
g_free(name);
}
create_unimplemented_device("pci.io", BONITO_PCIIO_BASE, 1 * MiB);
}
static void bonito_realize(PCIDevice *dev, Error **errp)
@ -619,6 +652,8 @@ static void bonito_realize(PCIDevice *dev, Error **errp)
PCIBonitoState *s = PCI_BONITO(dev);
SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost);
PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost);
BonitoState *bs = BONITO_PCI_HOST_BRIDGE(s->pcihost);
MemoryRegion *pcimem_alias = g_new(MemoryRegion, 1);
/*
* Bonito North Bridge, built on FPGA,
@ -644,15 +679,20 @@ static void bonito_realize(PCIDevice *dev, Error **errp)
sysbus_init_mmio(sysbus, &phb->data_mem);
sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE);
create_unimplemented_device("bonito", BONITO_REG_BASE, BONITO_REG_SIZE);
memory_region_init_io(&s->iomem_ldma, OBJECT(s), &bonito_ldma_ops, s,
"ldma", 0x100);
sysbus_init_mmio(sysbus, &s->iomem_ldma);
sysbus_mmio_map(sysbus, 3, 0xbfe00200);
sysbus_mmio_map(sysbus, 3, 0x1fe00200);
/* PCI copier */
memory_region_init_io(&s->iomem_cop, OBJECT(s), &bonito_cop_ops, s,
"cop", 0x100);
sysbus_init_mmio(sysbus, &s->iomem_cop);
sysbus_mmio_map(sysbus, 4, 0xbfe00300);
sysbus_mmio_map(sysbus, 4, 0x1fe00300);
create_unimplemented_device("ROMCS", BONITO_FLASH_BASE, 60 * MiB);
/* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */
memory_region_init_alias(&s->bonito_pciio, OBJECT(s), "isa_mmio",
@ -661,10 +701,25 @@ static void bonito_realize(PCIDevice *dev, Error **errp)
sysbus_mmio_map(sysbus, 5, BONITO_PCIIO_BASE);
/* add pci local io mapping */
memory_region_init_alias(&s->bonito_localio, OBJECT(s), "isa_mmio",
get_system_io(), 0, BONITO_DEV_SIZE);
memory_region_init_alias(&s->bonito_localio, OBJECT(s), "IOCS[0]",
get_system_io(), 0, 256 * KiB);
sysbus_init_mmio(sysbus, &s->bonito_localio);
sysbus_mmio_map(sysbus, 6, BONITO_DEV_BASE);
create_unimplemented_device("IOCS[1]", BONITO_DEV_BASE + 1 * 256 * KiB,
256 * KiB);
create_unimplemented_device("IOCS[2]", BONITO_DEV_BASE + 2 * 256 * KiB,
256 * KiB);
create_unimplemented_device("IOCS[3]", BONITO_DEV_BASE + 3 * 256 * KiB,
256 * KiB);
memory_region_init_alias(pcimem_alias, NULL, "pci.mem.alias",
&bs->pci_mem, 0, BONITO_PCIHI_SIZE);
memory_region_add_subregion(get_system_memory(),
BONITO_PCIHI_BASE, pcimem_alias);
create_unimplemented_device("PCI_2",
(hwaddr)BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE,
2 * GiB);
/* set the default value of north bridge pci config */
pci_set_word(dev->config + PCI_COMMAND, 0x0000);

2
tests/qtest/endianness-test.c
View File

@ -33,7 +33,7 @@ static const TestCase test_cases[] = {
{ "mips64", "pica61", 0x90000000, .bswap = true },
{ "mips64", "mips", 0x14000000, .bswap = true },
{ "mips64", "malta", 0x10000000, .bswap = true },
{ "mips64el", "fulong2e", 0x1fd00000 },
{ "mips64el", "fuloong2e", 0x1fd00000 },
{ "ppc", "g3beige", 0xfe000000, .bswap = true, .superio = "i82378" },
{ "ppc", "40p", 0x80000000, .bswap = true },
{ "ppc", "bamboo", 0xe8000000, .bswap = true, .superio = "i82378" },