mirror of https://github.com/proxmox/mirror_qemu
target-i386: convert gen_compute_eflags_c to TCG
Do the switch at translation time, converting the helper templates to TCG opcodes. In some cases CF can be computed with a single setcond, though others it may require a little more work. In the CC_OP_DYNAMIC case, compute the whole EFLAGS, same as for ZF/SF/PF. Reviewed-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Richard Henderson <rth@twiddle.net>master
parent
8115f11735
commit
06847f1f1a
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@ -869,17 +869,6 @@ static void gen_op_update_neg_cc(void)
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tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
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}
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/* compute eflags.C to reg */
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static void gen_compute_eflags_c(DisasContext *s, TCGv reg, bool inv)
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{
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gen_update_cc_op(s);
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gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_env, cpu_cc_op);
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tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
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if (inv) {
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tcg_gen_xori_tl(reg, reg, 1);
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}
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}
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/* compute all eflags to cc_src */
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static void gen_compute_eflags(DisasContext *s)
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{
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@ -892,6 +881,104 @@ static void gen_compute_eflags(DisasContext *s)
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tcg_gen_extu_i32_tl(cpu_cc_src, cpu_tmp2_i32);
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}
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/* compute eflags.C to reg */
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static void gen_compute_eflags_c(DisasContext *s, TCGv reg, bool inv)
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{
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TCGv t0, t1;
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int size;
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switch (s->cc_op) {
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case CC_OP_SUBB ... CC_OP_SUBQ:
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/* (DATA_TYPE)(CC_DST + CC_SRC) < (DATA_TYPE)CC_SRC */
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size = s->cc_op - CC_OP_SUBB;
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t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false);
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/* If no temporary was used, be careful not to alias t1 and t0. */
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t0 = TCGV_EQUAL(t1, cpu_cc_src) ? cpu_tmp0 : reg;
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tcg_gen_add_tl(t0, cpu_cc_dst, cpu_cc_src);
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gen_extu(size, t0);
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goto add_sub;
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case CC_OP_ADDB ... CC_OP_ADDQ:
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/* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */
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size = s->cc_op - CC_OP_ADDB;
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t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false);
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t0 = gen_ext_tl(reg, cpu_cc_dst, size, false);
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add_sub:
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tcg_gen_setcond_tl(inv ? TCG_COND_GEU : TCG_COND_LTU, reg, t0, t1);
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inv = false;
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break;
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case CC_OP_SBBB ... CC_OP_SBBQ:
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/* (DATA_TYPE)(CC_DST + CC_SRC + 1) <= (DATA_TYPE)CC_SRC */
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size = s->cc_op - CC_OP_SBBB;
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t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false);
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if (TCGV_EQUAL(t1, reg) && TCGV_EQUAL(reg, cpu_cc_src)) {
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tcg_gen_mov_tl(cpu_tmp0, cpu_cc_src);
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t1 = cpu_tmp0;
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}
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tcg_gen_add_tl(reg, cpu_cc_dst, cpu_cc_src);
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tcg_gen_addi_tl(reg, reg, 1);
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gen_extu(size, reg);
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t0 = reg;
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goto adc_sbb;
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case CC_OP_ADCB ... CC_OP_ADCQ:
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/* (DATA_TYPE)CC_DST <= (DATA_TYPE)CC_SRC */
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size = s->cc_op - CC_OP_ADCB;
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t1 = gen_ext_tl(cpu_tmp0, cpu_cc_src, size, false);
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t0 = gen_ext_tl(reg, cpu_cc_dst, size, false);
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adc_sbb:
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tcg_gen_setcond_tl(inv ? TCG_COND_GTU : TCG_COND_LEU, reg, t0, t1);
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inv = false;
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break;
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case CC_OP_LOGICB ... CC_OP_LOGICQ:
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tcg_gen_movi_tl(reg, 0);
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break;
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case CC_OP_INCB ... CC_OP_INCQ:
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case CC_OP_DECB ... CC_OP_DECQ:
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if (inv) {
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tcg_gen_xori_tl(reg, cpu_cc_src, 1);
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} else {
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tcg_gen_mov_tl(reg, cpu_cc_src);
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}
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inv = false;
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break;
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case CC_OP_SHLB ... CC_OP_SHLQ:
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/* (CC_SRC >> (DATA_BITS - 1)) & 1 */
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size = s->cc_op - CC_OP_SHLB;
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tcg_gen_shri_tl(reg, cpu_cc_src, (8 << size) - 1);
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tcg_gen_andi_tl(reg, reg, 1);
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break;
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case CC_OP_MULB ... CC_OP_MULQ:
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tcg_gen_setcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE,
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reg, cpu_cc_src, 0);
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inv = false;
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break;
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case CC_OP_EFLAGS:
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case CC_OP_SARB ... CC_OP_SARQ:
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/* CC_SRC & 1 */
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tcg_gen_andi_tl(reg, cpu_cc_src, 1);
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break;
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default:
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/* The need to compute only C from CC_OP_DYNAMIC is important
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in efficiently implementing e.g. INC at the start of a TB. */
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gen_update_cc_op(s);
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gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_env, cpu_cc_op);
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tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
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break;
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}
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if (inv) {
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tcg_gen_xori_tl(reg, reg, 1);
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}
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}
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/* compute eflags.P to reg */
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static void gen_compute_eflags_p(DisasContext *s, TCGv reg)
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{
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