mirror of https://github.com/proxmox/mirror_qemu
target/riscv: Add zext.h instructions to Zbb, removing pack/packu/packh
The 1.0.0 version of Zbb does not contain pack/packu/packh. However, a zext.h instruction is provided (built on pack/packh from pre-0.93 draft-B) is available. This commit adds zext.h and removes the pack* instructions. Note that the encodings for zext.h are different between RV32 and RV64, which is handled through REQUIRE_32BIT. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210911140016.834071-15-philipp.tomsich@vrull.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>master
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a1095bdcb0
commit
06dfa8a5c5
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@ -692,6 +692,9 @@ rori 01100 ............ 101 ..... 0010011 @sh
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sext_b 011000 000100 ..... 001 ..... 0010011 @r2
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sext_h 011000 000101 ..... 001 ..... 0010011 @r2
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xnor 0100000 .......... 100 ..... 0110011 @r
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# The encoding for zext.h differs between RV32 and RV64.
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# zext_h_32 denotes the RV32 variant.
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zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
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# *** RV64 Zbb Standard Extension (in addition to RV32 Zbb) ***
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clzw 0110000 00000 ..... 001 ..... 0011011 @r2
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@ -704,15 +707,14 @@ rev8_64 011010 111000 ..... 101 ..... 0010011 @r2
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rolw 0110000 .......... 001 ..... 0111011 @r
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roriw 0110000 .......... 101 ..... 0011011 @sh5
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rorw 0110000 .......... 101 ..... 0111011 @r
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# The encoding for zext.h differs between RV32 and RV64.
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# When executing on RV64, the encoding used in RV32 is an illegal
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# instruction, so we use different handler functions to differentiate.
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zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
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# *** RV32B Standard Extension ***
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pack 0000100 .......... 100 ..... 0110011 @r
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packu 0100100 .......... 100 ..... 0110011 @r
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packh 0000100 .......... 111 ..... 0110011 @r
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# *** RV64B Standard Extension (in addition to RV32B) ***
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packw 0000100 .......... 100 ..... 0111011 @r
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packuw 0100100 .......... 100 ..... 0111011 @r
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# *** RV32 Zbc Standard Extension ***
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clmul 0000101 .......... 001 ..... 0110011 @r
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@ -88,47 +88,6 @@ static bool trans_xnor(DisasContext *ctx, arg_xnor *a)
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return gen_arith(ctx, a, EXT_NONE, tcg_gen_eqv_tl);
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}
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static void gen_pack(TCGv ret, TCGv arg1, TCGv arg2)
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{
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tcg_gen_deposit_tl(ret, arg1, arg2,
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TARGET_LONG_BITS / 2,
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TARGET_LONG_BITS / 2);
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}
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static bool trans_pack(DisasContext *ctx, arg_pack *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_arith(ctx, a, EXT_NONE, gen_pack);
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}
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static void gen_packu(TCGv ret, TCGv arg1, TCGv arg2)
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{
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TCGv t = tcg_temp_new();
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tcg_gen_shri_tl(t, arg1, TARGET_LONG_BITS / 2);
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tcg_gen_deposit_tl(ret, arg2, t, 0, TARGET_LONG_BITS / 2);
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tcg_temp_free(t);
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}
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static bool trans_packu(DisasContext *ctx, arg_packu *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_arith(ctx, a, EXT_NONE, gen_packu);
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}
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static void gen_packh(TCGv ret, TCGv arg1, TCGv arg2)
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{
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TCGv t = tcg_temp_new();
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tcg_gen_ext8u_tl(t, arg2);
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tcg_gen_deposit_tl(ret, arg1, t, 8, TARGET_LONG_BITS - 8);
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tcg_temp_free(t);
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}
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static bool trans_packh(DisasContext *ctx, arg_packh *a)
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{
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REQUIRE_EXT(ctx, RVB);
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return gen_arith(ctx, a, EXT_NONE, gen_packh);
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}
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static bool trans_min(DisasContext *ctx, arg_min *a)
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{
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REQUIRE_ZBB(ctx);
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@ -336,6 +295,20 @@ GEN_TRANS_SHADD(1)
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GEN_TRANS_SHADD(2)
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GEN_TRANS_SHADD(3)
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static bool trans_zext_h_32(DisasContext *ctx, arg_zext_h_32 *a)
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{
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REQUIRE_32BIT(ctx);
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REQUIRE_ZBB(ctx);
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return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
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}
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static bool trans_zext_h_64(DisasContext *ctx, arg_zext_h_64 *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_ZBB(ctx);
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return gen_unary(ctx, a, EXT_NONE, tcg_gen_ext16u_tl);
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}
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static void gen_clzw(TCGv ret, TCGv arg1)
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{
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TCGv t = tcg_temp_new();
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@ -372,37 +345,6 @@ static bool trans_cpopw(DisasContext *ctx, arg_cpopw *a)
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return gen_unary(ctx, a, EXT_ZERO, tcg_gen_ctpop_tl);
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}
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static void gen_packw(TCGv ret, TCGv arg1, TCGv arg2)
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{
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TCGv t = tcg_temp_new();
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tcg_gen_ext16s_tl(t, arg2);
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tcg_gen_deposit_tl(ret, arg1, t, 16, 48);
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tcg_temp_free(t);
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}
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static bool trans_packw(DisasContext *ctx, arg_packw *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_EXT(ctx, RVB);
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return gen_arith(ctx, a, EXT_NONE, gen_packw);
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}
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static void gen_packuw(TCGv ret, TCGv arg1, TCGv arg2)
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{
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TCGv t = tcg_temp_new();
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tcg_gen_shri_tl(t, arg1, 16);
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tcg_gen_deposit_tl(ret, arg2, t, 0, 16);
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tcg_gen_ext32s_tl(ret, ret);
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tcg_temp_free(t);
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}
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static bool trans_packuw(DisasContext *ctx, arg_packuw *a)
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{
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REQUIRE_64BIT(ctx);
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REQUIRE_EXT(ctx, RVB);
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return gen_arith(ctx, a, EXT_NONE, gen_packuw);
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}
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static void gen_rorw(TCGv ret, TCGv arg1, TCGv arg2)
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{
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TCGv_i32 t1 = tcg_temp_new_i32();
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