mirror of https://github.com/proxmox/mirror_qemu
target/sh4: add missing CHECK_NOT_DELAY_SLOT
CHECK_NOT_DELAY_SLOT is correctly applied to the branch-related
instructions, but not to the PC-relative mov* instructions.
I verified the existence of an illegal slot exception on a SH7091 when
any of these instructions are attempted inside a delay slot.
This also matches the behavior described in the SH-4 ISA manual.
Signed-off-by: Zack Buhman <zack@buhman.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240407150705.5965-1-zack@buhman.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewd-by: Yoshinori Sato <ysato@users.sourceforge.jp>
(cherry picked from commit b754cb2dcd
)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
parent
733511728a
commit
0764b8a8e3
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@ -524,6 +524,7 @@ static void _decode_opc(DisasContext * ctx)
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tcg_gen_movi_i32(REG(B11_8), B7_0s);
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return;
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case 0x9000: /* mov.w @(disp,PC),Rn */
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CHECK_NOT_DELAY_SLOT
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{
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TCGv addr = tcg_constant_i32(ctx->base.pc_next + 4 + B7_0 * 2);
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tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
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@ -531,6 +532,7 @@ static void _decode_opc(DisasContext * ctx)
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}
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return;
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case 0xd000: /* mov.l @(disp,PC),Rn */
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CHECK_NOT_DELAY_SLOT
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{
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TCGv addr = tcg_constant_i32((ctx->base.pc_next + 4 + B7_0 * 4) & ~3);
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tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx,
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@ -1237,6 +1239,7 @@ static void _decode_opc(DisasContext * ctx)
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}
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return;
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case 0xc700: /* mova @(disp,PC),R0 */
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CHECK_NOT_DELAY_SLOT
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tcg_gen_movi_i32(REG(0), ((ctx->base.pc_next & 0xfffffffc) +
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4 + B7_0 * 4) & ~3);
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return;
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