mirror of https://github.com/proxmox/mirror_qemu
target/arm: Rebuild hflags for M-profile NVIC
Continue setting, but not relying upon, env->hflags. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-22-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>master
parent
873be7b69d
commit
080f2730cd
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@ -2251,7 +2251,7 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
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}
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}
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}
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}
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nvic_irq_update(s);
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nvic_irq_update(s);
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return MEMTX_OK;
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goto exit_ok;
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case 0x200 ... 0x23f: /* NVIC Set pend */
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case 0x200 ... 0x23f: /* NVIC Set pend */
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/* the special logic in armv7m_nvic_set_pending()
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/* the special logic in armv7m_nvic_set_pending()
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* is not needed since IRQs are never escalated
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* is not needed since IRQs are never escalated
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@ -2269,9 +2269,9 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
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}
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}
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}
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}
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nvic_irq_update(s);
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nvic_irq_update(s);
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return MEMTX_OK;
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goto exit_ok;
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case 0x300 ... 0x33f: /* NVIC Active */
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case 0x300 ... 0x33f: /* NVIC Active */
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return MEMTX_OK; /* R/O */
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goto exit_ok; /* R/O */
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case 0x400 ... 0x5ef: /* NVIC Priority */
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case 0x400 ... 0x5ef: /* NVIC Priority */
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startvec = (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */
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startvec = (offset - 0x400) + NVIC_FIRST_IRQ; /* vector # */
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@ -2281,10 +2281,10 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
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}
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}
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}
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}
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nvic_irq_update(s);
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nvic_irq_update(s);
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return MEMTX_OK;
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goto exit_ok;
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case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */
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case 0xd18 ... 0xd1b: /* System Handler Priority (SHPR1) */
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if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) {
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if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) {
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return MEMTX_OK;
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goto exit_ok;
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}
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}
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/* fall through */
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/* fall through */
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case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */
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case 0xd1c ... 0xd23: /* System Handler Priority (SHPR2, SHPR3) */
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@ -2299,10 +2299,10 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
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set_prio(s, hdlidx, sbank, newprio);
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set_prio(s, hdlidx, sbank, newprio);
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}
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}
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nvic_irq_update(s);
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nvic_irq_update(s);
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return MEMTX_OK;
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goto exit_ok;
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case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */
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case 0xd28 ... 0xd2b: /* Configurable Fault Status (CFSR) */
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if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) {
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if (!arm_feature(&s->cpu->env, ARM_FEATURE_M_MAIN)) {
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return MEMTX_OK;
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goto exit_ok;
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}
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}
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/* All bits are W1C, so construct 32 bit value with 0s in
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/* All bits are W1C, so construct 32 bit value with 0s in
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* the parts not written by the access size
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* the parts not written by the access size
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@ -2322,15 +2322,19 @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
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*/
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*/
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s->cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK);
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s->cpu->env.v7m.cfsr[M_REG_NS] &= ~(value & R_V7M_CFSR_BFSR_MASK);
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}
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}
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return MEMTX_OK;
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goto exit_ok;
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}
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}
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if (size == 4) {
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if (size == 4) {
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nvic_writel(s, offset, value, attrs);
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nvic_writel(s, offset, value, attrs);
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return MEMTX_OK;
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goto exit_ok;
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}
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}
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qemu_log_mask(LOG_GUEST_ERROR,
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qemu_log_mask(LOG_GUEST_ERROR,
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"NVIC: Bad write of size %d at offset 0x%x\n", size, offset);
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"NVIC: Bad write of size %d at offset 0x%x\n", size, offset);
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/* This is UNPREDICTABLE; treat as RAZ/WI */
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/* This is UNPREDICTABLE; treat as RAZ/WI */
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exit_ok:
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/* Ensure any changes made are reflected in the cached hflags. */
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arm_rebuild_hflags(&s->cpu->env);
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return MEMTX_OK;
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return MEMTX_OK;
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}
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}
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