mirror of https://github.com/proxmox/mirror_qemu
hw/mips_cmgcr: allow GCR base to be moved
Support moving the GCR base address & updating the CPU's CP0 CMGCRBase register appropriately. This is required if a platform needs to move its GCRs away from other memory, as the MIPS Boston development board does to avoid its flash memory. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>master
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796b288f7b
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08944be1d9
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@ -29,6 +29,20 @@ static inline bool is_gic_connected(MIPSGCRState *s)
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return s->gic_mr != NULL;
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return s->gic_mr != NULL;
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}
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}
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static inline void update_gcr_base(MIPSGCRState *gcr, uint64_t val)
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{
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CPUState *cpu;
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MIPSCPU *mips_cpu;
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gcr->gcr_base = val & GCR_BASE_GCRBASE_MSK;
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memory_region_set_address(&gcr->iomem, gcr->gcr_base);
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CPU_FOREACH(cpu) {
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mips_cpu = MIPS_CPU(cpu);
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mips_cpu->env.CP0_CMGCRBase = gcr->gcr_base >> 4;
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}
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}
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static inline void update_cpc_base(MIPSGCRState *gcr, uint64_t val)
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static inline void update_cpc_base(MIPSGCRState *gcr, uint64_t val)
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{
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{
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if (is_cpc_connected(gcr)) {
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if (is_cpc_connected(gcr)) {
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@ -117,6 +131,9 @@ static void gcr_write(void *opaque, hwaddr addr, uint64_t data, unsigned size)
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MIPSGCRVPState *other_vps = &gcr->vps[current_vps->other];
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MIPSGCRVPState *other_vps = &gcr->vps[current_vps->other];
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switch (addr) {
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switch (addr) {
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case GCR_BASE_OFS:
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update_gcr_base(gcr, data);
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break;
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case GCR_GIC_BASE_OFS:
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case GCR_GIC_BASE_OFS:
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update_gic_base(gcr, data);
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update_gic_base(gcr, data);
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break;
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break;
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@ -41,6 +41,9 @@
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#define GCR_L2_CONFIG_BYPASS_SHF 20
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#define GCR_L2_CONFIG_BYPASS_SHF 20
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#define GCR_L2_CONFIG_BYPASS_MSK ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF)
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#define GCR_L2_CONFIG_BYPASS_MSK ((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF)
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/* GCR_BASE register fields */
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#define GCR_BASE_GCRBASE_MSK 0xffffffff8000ULL
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/* GCR_GIC_BASE register fields */
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/* GCR_GIC_BASE register fields */
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#define GCR_GIC_BASE_GICEN_MSK 1
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#define GCR_GIC_BASE_GICEN_MSK 1
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#define GCR_GIC_BASE_GICBASE_MSK 0xFFFFFFFE0000ULL
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#define GCR_GIC_BASE_GICBASE_MSK 0xFFFFFFFE0000ULL
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