mirror of https://github.com/proxmox/mirror_qemu
target-arm: Convert cp15 crn=13 registers
Convert the cp15 crn=13 registers (FCSEIDR, CONTEXTIDR, and the ARM946 Trace Process Identifier Register). Signed-off-by: Peter Maydell <peter.maydell@linaro.org>master
parent
ecce5c3c90
commit
08de207bc5
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@ -63,6 +63,31 @@ static int dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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return 0;
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return 0;
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}
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}
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static int fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
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{
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if (env->cp15.c13_fcse != value) {
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/* Unlike real hardware the qemu TLB uses virtual addresses,
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* not modified virtual addresses, so this causes a TLB flush.
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*/
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tlb_flush(env, 1);
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env->cp15.c13_fcse = value;
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}
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return 0;
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}
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static int contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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if (env->cp15.c13_context != value && !arm_feature(env, ARM_FEATURE_MPU)) {
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/* For VMSA (when not using the LPAE long descriptor page table
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* format) this register includes the ASID, so do a TLB flush.
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* For PMSA it is purely a process ID and no action is needed.
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*/
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tlb_flush(env, 1);
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}
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env->cp15.c13_context = value;
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return 0;
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}
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static const ARMCPRegInfo cp_reginfo[] = {
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static const ARMCPRegInfo cp_reginfo[] = {
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/* DBGDIDR: just RAZ. In particular this means the "debug architecture
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/* DBGDIDR: just RAZ. In particular this means the "debug architecture
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* version" bits will read as a reserved value, which should cause
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* version" bits will read as a reserved value, which should cause
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@ -75,6 +100,12 @@ static const ARMCPRegInfo cp_reginfo[] = {
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.crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
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.crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
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.resetvalue = 0, .writefn = dacr_write },
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.resetvalue = 0, .writefn = dacr_write },
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{ .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
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.resetvalue = 0, .writefn = fcse_write },
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{ .name = "CONTEXTIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 1,
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.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
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.resetvalue = 0, .writefn = contextidr_write },
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REGINFO_SENTINEL
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REGINFO_SENTINEL
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};
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};
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@ -1769,27 +1800,6 @@ void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
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break;
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break;
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case 12: /* Reserved. */
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case 12: /* Reserved. */
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goto bad_reg;
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goto bad_reg;
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case 13: /* Process ID. */
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switch (op2) {
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case 0:
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/* Unlike real hardware the qemu TLB uses virtual addresses,
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not modified virtual addresses, so this causes a TLB flush.
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*/
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if (env->cp15.c13_fcse != val)
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tlb_flush(env, 1);
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env->cp15.c13_fcse = val;
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break;
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case 1:
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/* This changes the ASID, so do a TLB flush. */
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if (env->cp15.c13_context != val
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&& !arm_feature(env, ARM_FEATURE_MPU))
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tlb_flush(env, 0);
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env->cp15.c13_context = val;
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break;
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default:
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goto bad_reg;
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}
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break;
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case 15: /* Implementation specific. */
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case 15: /* Implementation specific. */
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if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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if (op2 == 0 && crm == 1) {
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if (op2 == 0 && crm == 1) {
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@ -2071,15 +2081,6 @@ uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
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case 11: /* TCM DMA control. */
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case 11: /* TCM DMA control. */
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case 12: /* Reserved. */
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case 12: /* Reserved. */
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goto bad_reg;
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goto bad_reg;
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case 13: /* Process ID. */
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switch (op2) {
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case 0:
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return env->cp15.c13_fcse;
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case 1:
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return env->cp15.c13_context;
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default:
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goto bad_reg;
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}
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case 15: /* Implementation specific. */
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case 15: /* Implementation specific. */
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if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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if (arm_feature(env, ARM_FEATURE_XSCALE)) {
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if (op2 == 0 && crm == 1)
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if (op2 == 0 && crm == 1)
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