mirror of https://github.com/proxmox/mirror_qemu
ppc patch queue for 2020-03-24
Here's a final pull request before the qemu-5.0 hard freeze. We have an implementation of the POWER9 forms of the slbia instruction, a small cleanup and a handful of assorted fixes. -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEdfRlhq5hpmzETofcbDjKyiDZs5IFAl55lr4ACgkQbDjKyiDZ s5LcrRAAyY7tEzJJnJUW+z9Hdmd0kqGbm1q7AwzX2Nb5X1ELbf8ZI7FoZ+dfehNi 7dQbnCwVtbQPQhnqoNMBZiHIxOS8lUa6O9iI+xKxgX4aDuIhH3s1VSIzbaWgimA5 Ho2i2uDr9p4DVRiy8INmZrdVMYuv6Le7jhILKYr6qQDFykWepi26IAN7PZ0UOnIT 4R78AfveLFSnvdFCLMED1WpGthaaEg9enjyv13gj9h+TkLRaHkvwjTRREEU880UP HmbN2FbdfNjxnkCIfRWbBwV/AjsHmW7OwMZeWKbGQkhtJ2bZ50+lGbagcebe8Enc GTqFYc4i96ulWVJHtH8sO/3cFXTnNoTZ7pj7+3IEjv8J/HpUd6jyJjF1rpXiFxcV 7+F0lJETgEPuRHsxs9Xkuhm0YisfIo3QUKEGRycty5lmMIb3Hr/3FcFepdzDbwtK PiDISncQcO5fymHxNBJKJMKziLPQ959/fngrtk+pgvzDg2CpKU2euWIc2k70SV/L 3f5SHr6CnHrMB21c0YHjNb5qY7JdFk5dr9rO5+yd9urI6ObMVztRB2Ign+HaFzDf BAYTj1YKKz8RkZcULHGdr/1kcr3/Hxj3bHPEocvsh5n1b8BsPAjQMLjNVxUv2ler UzbvQIZDsEKI/2bxA8ZSdMUftpEC6dd+k91tu1H/EumEidqk/Ag= =hGAI -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.0-20200324' into staging ppc patch queue for 2020-03-24 Here's a final pull request before the qemu-5.0 hard freeze. We have an implementation of the POWER9 forms of the slbia instruction, a small cleanup and a handful of assorted fixes. # gpg: Signature made Tue 24 Mar 2020 05:12:30 GMT # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-5.0-20200324: ppc/ppc405_boards: Remove unnecessary NULL check hw/ppc: Take QEMU lock when calling ppc_dcr_read/write() spapr: Fix memory leak in h_client_architecture_support() target/ppc: don't byte swap ELFv2 signal handler target/ppc: Fix ISA v3.0 (POWER9) slbia implementation target/ppc: Fix slbia TLB invalidation gap ppc/spapr: Set the effective address provided flag in mc error log. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>master
Peter Maydell
commit
09a98dd988
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@ -191,7 +191,7 @@ static void ref405ep_init(MachineState *machine)
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bios_size = 8 * MiB;
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pflash_cfi02_register((uint32_t)(-bios_size),
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"ef405ep.bios", bios_size,
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dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
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blk_by_legacy_dinfo(dinfo),
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64 * KiB, 1,
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2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
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1);
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@ -459,7 +459,7 @@ static void taihu_405ep_init(MachineState *machine)
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bios_size = 2 * MiB;
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pflash_cfi02_register(0xFFE00000,
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"taihu_405ep.bios", bios_size,
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dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
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blk_by_legacy_dinfo(dinfo),
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64 * KiB, 1,
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4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
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1);
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@ -494,7 +494,7 @@ static void taihu_405ep_init(MachineState *machine)
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if (dinfo) {
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bios_size = 32 * MiB;
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pflash_cfi02_register(0xfc000000, "taihu_405ep.flash", bios_size,
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dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
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blk_by_legacy_dinfo(dinfo),
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64 * KiB, 1,
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4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
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1);
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@ -243,6 +243,14 @@ struct rtas_event_log_v6_mc {
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#define RTAS_LOG_V6_MC_TLB_PARITY 1
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#define RTAS_LOG_V6_MC_TLB_MULTIHIT 2
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#define RTAS_LOG_V6_MC_TLB_INDETERMINATE 3
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/*
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* Per PAPR,
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* For UE error type, set bit 1 of sub_err_type to indicate effective addr is
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* provided. For other error types (SLB/ERAT/TLB), set bit 0 to indicate
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* same.
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*/
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#define RTAS_LOG_V6_MC_UE_EA_ADDR_PROVIDED 0x40
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#define RTAS_LOG_V6_MC_EA_ADDR_PROVIDED 0x80
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uint8_t reserved_1[6];
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uint64_t effective_address;
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uint64_t logical_address;
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@ -726,6 +734,22 @@ void spapr_hotplug_req_remove_by_count_indexed(SpaprDrcType drc_type,
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RTAS_LOG_V6_HP_ACTION_REMOVE, drc_type, &drc_id);
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}
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static void spapr_mc_set_ea_provided_flag(struct mc_extended_log *ext_elog)
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{
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switch (ext_elog->mc.error_type) {
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case RTAS_LOG_V6_MC_TYPE_UE:
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ext_elog->mc.sub_err_type |= RTAS_LOG_V6_MC_UE_EA_ADDR_PROVIDED;
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break;
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case RTAS_LOG_V6_MC_TYPE_SLB:
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case RTAS_LOG_V6_MC_TYPE_ERAT:
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case RTAS_LOG_V6_MC_TYPE_TLB:
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ext_elog->mc.sub_err_type |= RTAS_LOG_V6_MC_EA_ADDR_PROVIDED;
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break;
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default:
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break;
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}
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}
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static uint32_t spapr_mce_get_elog_type(PowerPCCPU *cpu, bool recovered,
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struct mc_extended_log *ext_elog)
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{
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@ -751,6 +775,7 @@ static uint32_t spapr_mce_get_elog_type(PowerPCCPU *cpu, bool recovered,
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ext_elog->mc.sub_err_type = mc_derror_table[i].error_subtype;
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if (mc_derror_table[i].dar_valid) {
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ext_elog->mc.effective_address = cpu_to_be64(env->spr[SPR_DAR]);
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spapr_mc_set_ea_provided_flag(ext_elog);
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}
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summary |= mc_derror_table[i].initiator
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@ -769,6 +794,7 @@ static uint32_t spapr_mce_get_elog_type(PowerPCCPU *cpu, bool recovered,
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ext_elog->mc.sub_err_type = mc_ierror_table[i].error_subtype;
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if (mc_ierror_table[i].nip_valid) {
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ext_elog->mc.effective_address = cpu_to_be64(env->nip);
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spapr_mc_set_ea_provided_flag(ext_elog);
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}
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summary |= mc_ierror_table[i].initiator
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@ -1726,6 +1726,7 @@ static target_ulong h_client_architecture_support(PowerPCCPU *cpu,
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}
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ov5_guest = spapr_ovec_parse_vector(ov_table, 5);
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if (!ov5_guest) {
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spapr_ovec_cleanup(ov1_guest);
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warn_report("guest didn't provide option vector 5");
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return H_PARAMETER;
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}
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@ -567,10 +567,8 @@ void setup_rt_frame(int sig, struct target_sigaction *ka,
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env->nip = tswapl(handler->entry);
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env->gpr[2] = tswapl(handler->toc);
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} else {
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/* ELFv2 PPC64 function pointers are entry points, but R12
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* must also be set */
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env->nip = tswapl((target_ulong) ka->_sa_handler);
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env->gpr[12] = env->nip;
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/* ELFv2 PPC64 function pointers are entry points. R12 must also be set. */
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env->gpr[12] = env->nip = ka->_sa_handler;
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}
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#else
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env->nip = (target_ulong) ka->_sa_handler;
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@ -614,7 +614,7 @@ DEF_HELPER_FLAGS_3(store_slb, TCG_CALL_NO_RWG, void, env, tl, tl)
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DEF_HELPER_2(load_slb_esid, tl, env, tl)
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DEF_HELPER_2(load_slb_vsid, tl, env, tl)
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DEF_HELPER_2(find_slb_vsid, tl, env, tl)
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DEF_HELPER_FLAGS_1(slbia, TCG_CALL_NO_RWG, void, env)
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DEF_HELPER_FLAGS_2(slbia, TCG_CALL_NO_RWG, void, env, i32)
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DEF_HELPER_FLAGS_2(slbie, TCG_CALL_NO_RWG, void, env, tl)
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DEF_HELPER_FLAGS_2(slbieg, TCG_CALL_NO_RWG, void, env, tl)
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#endif
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@ -95,24 +95,75 @@ void dump_slb(PowerPCCPU *cpu)
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}
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}
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void helper_slbia(CPUPPCState *env)
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void helper_slbia(CPUPPCState *env, uint32_t ih)
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{
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PowerPCCPU *cpu = env_archcpu(env);
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int starting_entry;
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int n;
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/* XXX: Warning: slbia never invalidates the first segment */
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for (n = 1; n < cpu->hash64_opts->slb_size; n++) {
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/*
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* slbia must always flush all TLB (which is equivalent to ERAT in ppc
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* architecture). Matching on SLB_ESID_V is not good enough, because slbmte
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* can overwrite a valid SLB without flushing its lookaside information.
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*
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* It would be possible to keep the TLB in synch with the SLB by flushing
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* when a valid entry is overwritten by slbmte, and therefore slbia would
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* not have to flush unless it evicts a valid SLB entry. However it is
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* expected that slbmte is more common than slbia, and slbia is usually
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* going to evict valid SLB entries, so that tradeoff is unlikely to be a
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* good one.
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*
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* ISA v2.05 introduced IH field with values 0,1,2,6. These all invalidate
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* the same SLB entries (everything but entry 0), but differ in what
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* "lookaside information" is invalidated. TCG can ignore this and flush
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* everything.
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*
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* ISA v3.0 introduced additional values 3,4,7, which change what SLBs are
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* invalidated.
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*/
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env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
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starting_entry = 1; /* default for IH=0,1,2,6 */
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if (env->mmu_model == POWERPC_MMU_3_00) {
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switch (ih) {
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case 0x7:
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/* invalidate no SLBs, but all lookaside information */
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return;
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case 0x3:
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case 0x4:
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/* also considers SLB entry 0 */
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starting_entry = 0;
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break;
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case 0x5:
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/* treat undefined values as ih==0, and warn */
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qemu_log_mask(LOG_GUEST_ERROR,
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"slbia undefined IH field %u.\n", ih);
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break;
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default:
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/* 0,1,2,6 */
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break;
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}
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}
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for (n = starting_entry; n < cpu->hash64_opts->slb_size; n++) {
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ppc_slb_t *slb = &env->slb[n];
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if (slb->esid & SLB_ESID_V) {
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slb->esid &= ~SLB_ESID_V;
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/*
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* XXX: given the fact that segment size is 256 MB or 1TB,
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* and we still don't have a tlb_flush_mask(env, n, mask)
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* in QEMU, we just invalidate all TLBs
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*/
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env->tlb_need_flush |= TLB_NEED_LOCAL_FLUSH;
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if (!(slb->esid & SLB_ESID_V)) {
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continue;
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}
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if (env->mmu_model == POWERPC_MMU_3_00) {
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if (ih == 0x3 && (slb->vsid & SLB_VSID_C) == 0) {
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/* preserves entries with a class value of 0 */
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continue;
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}
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}
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slb->esid &= ~SLB_ESID_V;
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}
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}
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@ -21,6 +21,7 @@
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#include "exec/helper-proto.h"
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#include "exec/exec-all.h"
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#include "qemu/log.h"
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#include "qemu/main-loop.h"
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/*****************************************************************************/
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/* SPR accesses */
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@ -167,13 +168,19 @@ target_ulong helper_load_dcr(CPUPPCState *env, target_ulong dcrn)
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raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
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POWERPC_EXCP_INVAL |
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POWERPC_EXCP_INVAL_INVAL, GETPC());
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} else if (unlikely(ppc_dcr_read(env->dcr_env,
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(uint32_t)dcrn, &val) != 0)) {
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qemu_log_mask(LOG_GUEST_ERROR, "DCR read error %d %03x\n",
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(uint32_t)dcrn, (uint32_t)dcrn);
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raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
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POWERPC_EXCP_INVAL |
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POWERPC_EXCP_PRIV_REG, GETPC());
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} else {
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int ret;
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qemu_mutex_lock_iothread();
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ret = ppc_dcr_read(env->dcr_env, (uint32_t)dcrn, &val);
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qemu_mutex_unlock_iothread();
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if (unlikely(ret != 0)) {
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qemu_log_mask(LOG_GUEST_ERROR, "DCR read error %d %03x\n",
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(uint32_t)dcrn, (uint32_t)dcrn);
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raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
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POWERPC_EXCP_INVAL |
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POWERPC_EXCP_PRIV_REG, GETPC());
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}
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}
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return val;
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}
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@ -185,12 +192,17 @@ void helper_store_dcr(CPUPPCState *env, target_ulong dcrn, target_ulong val)
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raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
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POWERPC_EXCP_INVAL |
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POWERPC_EXCP_INVAL_INVAL, GETPC());
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} else if (unlikely(ppc_dcr_write(env->dcr_env, (uint32_t)dcrn,
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(uint32_t)val) != 0)) {
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qemu_log_mask(LOG_GUEST_ERROR, "DCR write error %d %03x\n",
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(uint32_t)dcrn, (uint32_t)dcrn);
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raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
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POWERPC_EXCP_INVAL |
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POWERPC_EXCP_PRIV_REG, GETPC());
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} else {
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int ret;
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qemu_mutex_lock_iothread();
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ret = ppc_dcr_write(env->dcr_env, (uint32_t)dcrn, (uint32_t)val);
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qemu_mutex_unlock_iothread();
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if (unlikely(ret != 0)) {
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qemu_log_mask(LOG_GUEST_ERROR, "DCR write error %d %03x\n",
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(uint32_t)dcrn, (uint32_t)dcrn);
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raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM,
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POWERPC_EXCP_INVAL |
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POWERPC_EXCP_PRIV_REG, GETPC());
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}
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}
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}
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|
|
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@ -4997,9 +4997,12 @@ static void gen_slbia(DisasContext *ctx)
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#if defined(CONFIG_USER_ONLY)
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GEN_PRIV;
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#else
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||||
uint32_t ih = (ctx->opcode >> 21) & 0x7;
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TCGv_i32 t0 = tcg_const_i32(ih);
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CHK_SV;
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||||
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gen_helper_slbia(cpu_env);
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||||
gen_helper_slbia(cpu_env, t0);
|
||||
#endif /* defined(CONFIG_USER_ONLY) */
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||||
}
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||||
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||||
|
|
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|||
Loading…
Reference in New Issue