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tests: q35: MCH: add default SMBASE SMRAM lock test 

test lockable SMRAM at default SMBASE feature, introduced by
patch "q35: implement 128K SMRAM at default SMBASE address"

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Message-Id: <1575899217-333105-1-git-send-email-imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
master
Igor Mammedov 2019-12-09 14:46:57 +01:00 committed by Michael S. Tsirkin
parent f404220e27
commit 0cdd3eae15
1 changed files with 105 additions and 0 deletions
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105
tests/qtest/q35-test.c
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@ -186,6 +186,109 @@ static void test_tseg_size(const void *data)
qtest_quit(qts);
}
#define SMBASE 0x30000
#define SMRAM_TEST_PATTERN 0x32
#define SMRAM_TEST_RESET_PATTERN 0x23
static void test_smram_smbase_lock(void)
{
QPCIBus *pcibus;
QPCIDevice *pcidev;
QDict *response;
QTestState *qts;
int i;
qts = qtest_init("-M q35");
pcibus = qpci_new_pc(qts, NULL);
g_assert(pcibus != NULL);
pcidev = qpci_device_find(pcibus, 0);
g_assert(pcidev != NULL);
/* check that SMRAM is not enabled by default */
g_assert(qpci_config_readb(pcidev, MCH_HOST_BRIDGE_F_SMBASE) == 0);
qtest_writeb(qts, SMBASE, SMRAM_TEST_PATTERN);
g_assert_cmpint(qtest_readb(qts, SMBASE), ==, SMRAM_TEST_PATTERN);
/* check that writing junk to 0x9c before before negotiating is ignored */
for (i = 0; i < 0xff; i++) {
qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_F_SMBASE, i);
g_assert(qpci_config_readb(pcidev, MCH_HOST_BRIDGE_F_SMBASE) == 0);
}
/* enable SMRAM at SMBASE */
qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_F_SMBASE, 0xff);
g_assert(qpci_config_readb(pcidev, MCH_HOST_BRIDGE_F_SMBASE) == 0x01);
/* lock SMRAM at SMBASE */
qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_F_SMBASE, 0x02);
g_assert(qpci_config_readb(pcidev, MCH_HOST_BRIDGE_F_SMBASE) == 0x02);
/* check that SMRAM at SMBASE is locked and can't be unlocked */
g_assert_cmpint(qtest_readb(qts, SMBASE), ==, 0xff);
for (i = 0; i <= 0xff; i++) {
/* make sure register is immutable */
qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_F_SMBASE, i);
g_assert(qpci_config_readb(pcidev, MCH_HOST_BRIDGE_F_SMBASE) == 0x02);
/* RAM access should go into black hole */
qtest_writeb(qts, SMBASE, SMRAM_TEST_PATTERN);
g_assert_cmpint(qtest_readb(qts, SMBASE), ==, 0xff);
}
/* reset */
response = qtest_qmp(qts, "{'execute': 'system_reset', 'arguments': {} }");
g_assert(response);
g_assert(!qdict_haskey(response, "error"));
qobject_unref(response);
/* check RAM at SMBASE is available after reset */
g_assert_cmpint(qtest_readb(qts, SMBASE), ==, SMRAM_TEST_PATTERN);
g_assert(qpci_config_readb(pcidev, MCH_HOST_BRIDGE_F_SMBASE) == 0);
qtest_writeb(qts, SMBASE, SMRAM_TEST_RESET_PATTERN);
g_assert_cmpint(qtest_readb(qts, SMBASE), ==, SMRAM_TEST_RESET_PATTERN);
g_free(pcidev);
qpci_free_pc(pcibus);
qtest_quit(qts);
}
static void test_without_smram_base(void)
{
QPCIBus *pcibus;
QPCIDevice *pcidev;
QTestState *qts;
int i;
qts = qtest_init("-M pc-q35-4.1");
pcibus = qpci_new_pc(qts, NULL);
g_assert(pcibus != NULL);
pcidev = qpci_device_find(pcibus, 0);
g_assert(pcidev != NULL);
/* check that RAM is accessible */
qtest_writeb(qts, SMBASE, SMRAM_TEST_PATTERN);
g_assert_cmpint(qtest_readb(qts, SMBASE), ==, SMRAM_TEST_PATTERN);
/* check that writing to 0x9c succeeds */
for (i = 0; i <= 0xff; i++) {
qpci_config_writeb(pcidev, MCH_HOST_BRIDGE_F_SMBASE, i);
g_assert(qpci_config_readb(pcidev, MCH_HOST_BRIDGE_F_SMBASE) == i);
}
/* check that RAM is still accessible */
qtest_writeb(qts, SMBASE, SMRAM_TEST_PATTERN + 1);
g_assert_cmpint(qtest_readb(qts, SMBASE), ==, (SMRAM_TEST_PATTERN + 1));
g_free(pcidev);
qpci_free_pc(pcibus);
qtest_quit(qts);
}
int main(int argc, char **argv)
{
g_test_init(&argc, &argv, NULL);
@ -197,5 +300,7 @@ int main(int argc, char **argv)
qtest_add_data_func("/q35/tseg-size/8mb", &tseg_8mb, test_tseg_size);
qtest_add_data_func("/q35/tseg-size/ext/16mb", &tseg_ext_16mb,
test_tseg_size);
qtest_add_func("/q35/smram/smbase_lock", test_smram_smbase_lock);
qtest_add_func("/q35/smram/legacy_smbase", test_without_smram_base);
return g_test_run();
}