mirror of https://github.com/proxmox/mirror_qemu
target-microblaze: Make compute_ldst_addr always use a temp
Make compute_ldst_addr always use a temp. This simplifies the code a bit in preparation for adding support for 64bit addresses. No functional change. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>master
parent
a2de5ca451
commit
0dc4af5c1a
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@ -848,7 +848,7 @@ static void dec_imm(DisasContext *dc)
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dc->clear_imm = 0;
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dc->clear_imm = 0;
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}
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}
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static inline TCGv_i32 *compute_ldst_addr(DisasContext *dc, TCGv_i32 *t)
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static inline void compute_ldst_addr(DisasContext *dc, TCGv_i32 *t)
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{
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{
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bool extimm = dc->tb_flags & IMM_FLAG;
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bool extimm = dc->tb_flags & IMM_FLAG;
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/* Should be set to true if r1 is used by loadstores. */
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/* Should be set to true if r1 is used by loadstores. */
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@ -861,47 +861,47 @@ static inline TCGv_i32 *compute_ldst_addr(DisasContext *dc, TCGv_i32 *t)
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/* Treat the common cases first. */
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/* Treat the common cases first. */
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if (!dc->type_b) {
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if (!dc->type_b) {
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/* If any of the regs is r0, return a ptr to the other. */
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/* If any of the regs is r0, set t to the value of the other reg. */
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if (dc->ra == 0) {
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if (dc->ra == 0) {
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return &cpu_R[dc->rb];
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tcg_gen_mov_i32(*t, cpu_R[dc->rb]);
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return;
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} else if (dc->rb == 0) {
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} else if (dc->rb == 0) {
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return &cpu_R[dc->ra];
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tcg_gen_mov_i32(*t, cpu_R[dc->ra]);
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return;
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}
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}
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if (dc->rb == 1 && dc->cpu->cfg.stackprot) {
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if (dc->rb == 1 && dc->cpu->cfg.stackprot) {
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stackprot = true;
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stackprot = true;
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}
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}
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*t = tcg_temp_new_i32();
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tcg_gen_add_i32(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
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tcg_gen_add_i32(*t, cpu_R[dc->ra], cpu_R[dc->rb]);
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if (stackprot) {
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if (stackprot) {
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gen_helper_stackprot(cpu_env, *t);
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gen_helper_stackprot(cpu_env, *t);
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}
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}
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return t;
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return;
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}
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}
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/* Immediate. */
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/* Immediate. */
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if (!extimm) {
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if (!extimm) {
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if (dc->imm == 0) {
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if (dc->imm == 0) {
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return &cpu_R[dc->ra];
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tcg_gen_mov_i32(*t, cpu_R[dc->ra]);
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return;
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}
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}
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*t = tcg_temp_new_i32();
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tcg_gen_movi_i32(*t, (int32_t)((int16_t)dc->imm));
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tcg_gen_movi_i32(*t, (int32_t)((int16_t)dc->imm));
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tcg_gen_add_i32(*t, cpu_R[dc->ra], *t);
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tcg_gen_add_i32(*t, cpu_R[dc->ra], *t);
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} else {
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} else {
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*t = tcg_temp_new_i32();
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tcg_gen_add_i32(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
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tcg_gen_add_i32(*t, cpu_R[dc->ra], *(dec_alu_op_b(dc)));
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}
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}
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if (stackprot) {
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if (stackprot) {
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gen_helper_stackprot(cpu_env, *t);
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gen_helper_stackprot(cpu_env, *t);
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}
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}
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return t;
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return;
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}
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}
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static void dec_load(DisasContext *dc)
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static void dec_load(DisasContext *dc)
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{
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{
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TCGv_i32 t, v, *addr;
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TCGv_i32 v, addr;
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unsigned int size;
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unsigned int size;
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bool rev = false, ex = false;
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bool rev = false, ex = false;
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TCGMemOp mop;
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TCGMemOp mop;
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@ -928,7 +928,8 @@ static void dec_load(DisasContext *dc)
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ex ? "x" : "");
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ex ? "x" : "");
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t_sync_flags(dc);
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t_sync_flags(dc);
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addr = compute_ldst_addr(dc, &t);
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addr = tcg_temp_new_i32();
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compute_ldst_addr(dc, &addr);
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/*
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/*
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* When doing reverse accesses we need to do two things.
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* When doing reverse accesses we need to do two things.
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@ -947,17 +948,10 @@ static void dec_load(DisasContext *dc)
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11 -> 00 */
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11 -> 00 */
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TCGv_i32 low = tcg_temp_new_i32();
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TCGv_i32 low = tcg_temp_new_i32();
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/* Force addr into the temp. */
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tcg_gen_andi_i32(low, addr, 3);
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if (addr != &t) {
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t = tcg_temp_new_i32();
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tcg_gen_mov_i32(t, *addr);
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addr = &t;
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}
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tcg_gen_andi_i32(low, t, 3);
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tcg_gen_sub_i32(low, tcg_const_i32(3), low);
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tcg_gen_sub_i32(low, tcg_const_i32(3), low);
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tcg_gen_andi_i32(t, t, ~3);
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tcg_gen_andi_i32(addr, addr, ~3);
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tcg_gen_or_i32(t, t, low);
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tcg_gen_or_i32(addr, addr, low);
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tcg_temp_free_i32(low);
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tcg_temp_free_i32(low);
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break;
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break;
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}
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}
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@ -965,14 +959,7 @@ static void dec_load(DisasContext *dc)
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case 2:
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case 2:
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/* 00 -> 10
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/* 00 -> 10
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10 -> 00. */
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10 -> 00. */
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/* Force addr into the temp. */
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tcg_gen_xori_i32(addr, addr, 2);
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if (addr != &t) {
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t = tcg_temp_new_i32();
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tcg_gen_xori_i32(t, *addr, 2);
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addr = &t;
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} else {
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tcg_gen_xori_i32(t, t, 2);
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}
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break;
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break;
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default:
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default:
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cpu_abort(CPU(dc->cpu), "Invalid reverse size\n");
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cpu_abort(CPU(dc->cpu), "Invalid reverse size\n");
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@ -982,13 +969,7 @@ static void dec_load(DisasContext *dc)
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/* lwx does not throw unaligned access errors, so force alignment */
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/* lwx does not throw unaligned access errors, so force alignment */
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if (ex) {
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if (ex) {
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/* Force addr into the temp. */
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tcg_gen_andi_i32(addr, addr, ~3);
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if (addr != &t) {
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t = tcg_temp_new_i32();
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tcg_gen_mov_i32(t, *addr);
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addr = &t;
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}
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tcg_gen_andi_i32(t, t, ~3);
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}
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}
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/* If we get a fault on a dslot, the jmpstate better be in sync. */
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/* If we get a fault on a dslot, the jmpstate better be in sync. */
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@ -1002,16 +983,16 @@ static void dec_load(DisasContext *dc)
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* address and if that succeeds we write into the destination reg.
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* address and if that succeeds we write into the destination reg.
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*/
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*/
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v = tcg_temp_new_i32();
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v = tcg_temp_new_i32();
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tcg_gen_qemu_ld_i32(v, *addr, cpu_mmu_index(&dc->cpu->env, false), mop);
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tcg_gen_qemu_ld_i32(v, addr, cpu_mmu_index(&dc->cpu->env, false), mop);
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if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
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if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
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tcg_gen_movi_i32(cpu_SR[SR_PC], dc->pc);
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tcg_gen_movi_i32(cpu_SR[SR_PC], dc->pc);
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gen_helper_memalign(cpu_env, *addr, tcg_const_i32(dc->rd),
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gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd),
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tcg_const_i32(0), tcg_const_i32(size - 1));
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tcg_const_i32(0), tcg_const_i32(size - 1));
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}
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}
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if (ex) {
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if (ex) {
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tcg_gen_mov_i32(env_res_addr, *addr);
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tcg_gen_mov_i32(env_res_addr, addr);
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tcg_gen_mov_i32(env_res_val, v);
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tcg_gen_mov_i32(env_res_val, v);
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}
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}
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if (dc->rd) {
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if (dc->rd) {
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@ -1024,13 +1005,12 @@ static void dec_load(DisasContext *dc)
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write_carryi(dc, 0);
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write_carryi(dc, 0);
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}
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}
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if (addr == &t)
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tcg_temp_free_i32(addr);
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tcg_temp_free_i32(t);
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}
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}
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static void dec_store(DisasContext *dc)
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static void dec_store(DisasContext *dc)
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{
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{
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TCGv_i32 t, *addr, swx_addr;
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TCGv_i32 addr;
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TCGLabel *swx_skip = NULL;
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TCGLabel *swx_skip = NULL;
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unsigned int size;
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unsigned int size;
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bool rev = false, ex = false;
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bool rev = false, ex = false;
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@ -1059,21 +1039,19 @@ static void dec_store(DisasContext *dc)
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t_sync_flags(dc);
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t_sync_flags(dc);
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/* If we get a fault on a dslot, the jmpstate better be in sync. */
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/* If we get a fault on a dslot, the jmpstate better be in sync. */
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sync_jmpstate(dc);
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sync_jmpstate(dc);
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addr = compute_ldst_addr(dc, &t);
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/* SWX needs a temp_local. */
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addr = ex ? tcg_temp_local_new_i32() : tcg_temp_new_i32();
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compute_ldst_addr(dc, &addr);
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swx_addr = tcg_temp_local_new_i32();
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if (ex) { /* swx */
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if (ex) { /* swx */
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TCGv_i32 tval;
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TCGv_i32 tval;
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/* Force addr into the swx_addr. */
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tcg_gen_mov_i32(swx_addr, *addr);
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addr = &swx_addr;
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/* swx does not throw unaligned access errors, so force alignment */
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/* swx does not throw unaligned access errors, so force alignment */
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tcg_gen_andi_i32(swx_addr, swx_addr, ~3);
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tcg_gen_andi_i32(addr, addr, ~3);
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write_carryi(dc, 1);
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write_carryi(dc, 1);
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swx_skip = gen_new_label();
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swx_skip = gen_new_label();
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tcg_gen_brcond_i32(TCG_COND_NE, env_res_addr, swx_addr, swx_skip);
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tcg_gen_brcond_i32(TCG_COND_NE, env_res_addr, addr, swx_skip);
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/* Compare the value loaded at lwx with current contents of
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/* Compare the value loaded at lwx with current contents of
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the reserved location.
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the reserved location.
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@ -1081,8 +1059,8 @@ static void dec_store(DisasContext *dc)
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this compare and the following write to be atomic. For user
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this compare and the following write to be atomic. For user
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emulation we need to add atomicity between threads. */
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emulation we need to add atomicity between threads. */
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tval = tcg_temp_new_i32();
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tval = tcg_temp_new_i32();
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tcg_gen_qemu_ld_i32(tval, swx_addr, cpu_mmu_index(&dc->cpu->env, false),
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tcg_gen_qemu_ld_i32(tval, addr, cpu_mmu_index(&dc->cpu->env, false),
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MO_TEUL);
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MO_TEUL);
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tcg_gen_brcond_i32(TCG_COND_NE, env_res_val, tval, swx_skip);
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tcg_gen_brcond_i32(TCG_COND_NE, env_res_val, tval, swx_skip);
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write_carryi(dc, 0);
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write_carryi(dc, 0);
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tcg_temp_free_i32(tval);
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tcg_temp_free_i32(tval);
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@ -1099,17 +1077,10 @@ static void dec_store(DisasContext *dc)
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11 -> 00 */
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11 -> 00 */
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TCGv_i32 low = tcg_temp_new_i32();
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TCGv_i32 low = tcg_temp_new_i32();
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/* Force addr into the temp. */
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tcg_gen_andi_i32(low, addr, 3);
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if (addr != &t) {
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t = tcg_temp_new_i32();
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tcg_gen_mov_i32(t, *addr);
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addr = &t;
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}
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tcg_gen_andi_i32(low, t, 3);
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tcg_gen_sub_i32(low, tcg_const_i32(3), low);
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tcg_gen_sub_i32(low, tcg_const_i32(3), low);
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tcg_gen_andi_i32(t, t, ~3);
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tcg_gen_andi_i32(addr, addr, ~3);
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tcg_gen_or_i32(t, t, low);
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tcg_gen_or_i32(addr, addr, low);
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tcg_temp_free_i32(low);
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tcg_temp_free_i32(low);
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break;
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break;
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}
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}
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@ -1118,20 +1089,14 @@ static void dec_store(DisasContext *dc)
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/* 00 -> 10
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/* 00 -> 10
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10 -> 00. */
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10 -> 00. */
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/* Force addr into the temp. */
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/* Force addr into the temp. */
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if (addr != &t) {
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tcg_gen_xori_i32(addr, addr, 2);
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t = tcg_temp_new_i32();
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tcg_gen_xori_i32(t, *addr, 2);
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addr = &t;
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} else {
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tcg_gen_xori_i32(t, t, 2);
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}
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break;
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break;
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default:
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default:
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cpu_abort(CPU(dc->cpu), "Invalid reverse size\n");
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cpu_abort(CPU(dc->cpu), "Invalid reverse size\n");
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break;
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break;
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}
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}
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}
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}
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tcg_gen_qemu_st_i32(cpu_R[dc->rd], *addr,
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tcg_gen_qemu_st_i32(cpu_R[dc->rd], addr,
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cpu_mmu_index(&dc->cpu->env, false), mop);
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cpu_mmu_index(&dc->cpu->env, false), mop);
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/* Verify alignment if needed. */
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/* Verify alignment if needed. */
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@ -1143,17 +1108,15 @@ static void dec_store(DisasContext *dc)
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* the alignment checks in between the probe and the mem
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* the alignment checks in between the probe and the mem
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* access.
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* access.
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*/
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*/
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gen_helper_memalign(cpu_env, *addr, tcg_const_i32(dc->rd),
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gen_helper_memalign(cpu_env, addr, tcg_const_i32(dc->rd),
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tcg_const_i32(1), tcg_const_i32(size - 1));
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tcg_const_i32(1), tcg_const_i32(size - 1));
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}
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}
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if (ex) {
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if (ex) {
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gen_set_label(swx_skip);
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gen_set_label(swx_skip);
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}
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}
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tcg_temp_free_i32(swx_addr);
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if (addr == &t)
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tcg_temp_free_i32(addr);
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tcg_temp_free_i32(t);
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}
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}
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static inline void eval_cc(DisasContext *dc, unsigned int cc,
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static inline void eval_cc(DisasContext *dc, unsigned int cc,
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