mirror of https://github.com/proxmox/mirror_qemu
target/mips: Fix DEXTRV_S.H DSP opcode
While for the DEXTR_S.H opcode:
"The shift argument is provided in the instruction."
For the DEXTRV_S.H opcode we have:
"The five least-significant bits of register rs provide the
shift argument, interpreted as a five-bit unsigned integer;
the remaining bits in rs are ignored."
While 't1' contains the 'rs' register content (the shift value
for DEXTR_S.H), we need to load the value of 'rs' for DEXTRV_S.H.
We can directly use the v1_t TCG register which already contains
this shift value.
Fixes: b53371ed5d
("target-mips: Add ASE DSP accumulator instructions")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211013215652.1764551-1-f4bug@amsat.org>
master
parent
d2db0f729d
commit
0e235827de
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@ -13796,8 +13796,7 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2,
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break;
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case OPC_DEXTRV_S_H:
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tcg_gen_movi_tl(t0, v2);
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tcg_gen_movi_tl(t1, v1);
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gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, cpu_env);
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gen_helper_dextr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env);
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break;
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case OPC_DEXTRV_L:
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tcg_gen_movi_tl(t0, v2);
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